clk: tegra: pll: Adjust vco_min if SDM present
This code makes use of the SDM fractional divider if present to
constrain the allowable programming range of the PLL divider register
bitfields to take advantage of higher frequency granularity that can
be induced by the SDM divider.
Based on original work by Aleksandr Frid <afrid@nvidia.com>
Signed-off-by: Bill Huang <bilhuang@nvidia.com>
Signed-off-by: Rhyland Klein <rklein@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
diff --git a/drivers/clk/tegra/clk-pll.c b/drivers/clk/tegra/clk-pll.c
index 420ca82..66da418 100644
--- a/drivers/clk/tegra/clk-pll.c
+++ b/drivers/clk/tegra/clk-pll.c
@@ -1621,6 +1621,10 @@
pll_params->vco_min = _clip_vco_min(pll_params->vco_min, parent_rate);
+ if (pll_params->adjust_vco)
+ pll_params->vco_min = pll_params->adjust_vco(pll_params,
+ parent_rate);
+
err = _setup_dynamic_ramp(pll_params, clk_base, parent_rate);
if (err)
return ERR_PTR(err);
@@ -1659,6 +1663,10 @@
pll_params->vco_min = _clip_vco_min(pll_params->vco_min, parent_rate);
+ if (pll_params->adjust_vco)
+ pll_params->vco_min = pll_params->adjust_vco(pll_params,
+ parent_rate);
+
pll = _tegra_init_pll(clk_base, pmc, pll_params, lock);
if (IS_ERR(pll))
return ERR_CAST(pll);
@@ -1715,6 +1723,10 @@
pll_params->vco_min = _clip_vco_min(pll_params->vco_min, parent_rate);
+ if (pll_params->adjust_vco)
+ pll_params->vco_min = pll_params->adjust_vco(pll_params,
+ parent_rate);
+
pll_params->flags |= TEGRA_PLL_BYPASS;
pll_params->flags |= TEGRA_PLLM;
pll = _tegra_init_pll(clk_base, pmc, pll_params, lock);
@@ -2121,6 +2133,10 @@
pll_params->vco_min = _clip_vco_min(pll_params->vco_min, parent_rate);
+ if (pll_params->adjust_vco)
+ pll_params->vco_min = pll_params->adjust_vco(pll_params,
+ parent_rate);
+
pll_params->flags |= TEGRA_PLL_BYPASS;
pll = _tegra_init_pll(clk_base, pmc, pll_params, lock);
if (IS_ERR(pll))
@@ -2158,6 +2174,10 @@
pll_params->vco_min = _clip_vco_min(pll_params->vco_min, parent_rate);
+ if (pll_params->adjust_vco)
+ pll_params->vco_min = pll_params->adjust_vco(pll_params,
+ parent_rate);
+
pll = _tegra_init_pll(clk_base, pmc, pll_params, lock);
if (IS_ERR(pll))
return ERR_CAST(pll);
@@ -2205,6 +2225,10 @@
pll_params->vco_min = _clip_vco_min(pll_params->vco_min, parent_rate);
+ if (pll_params->adjust_vco)
+ pll_params->vco_min = pll_params->adjust_vco(pll_params,
+ parent_rate);
+
/* initialize PLL to minimum rate */
cfg.m = _pll_fixed_mdiv(pll_params, parent_rate);
@@ -2269,6 +2293,10 @@
pll_params->vco_min = _clip_vco_min(pll_params->vco_min, parent_rate);
+ if (pll_params->adjust_vco)
+ pll_params->vco_min = pll_params->adjust_vco(pll_params,
+ parent_rate);
+
pll_params->flags |= TEGRA_PLL_BYPASS;
pll_params->flags |= TEGRA_PLLMB;
pll = _tegra_init_pll(clk_base, pmc, pll_params, lock);
diff --git a/drivers/clk/tegra/clk.h b/drivers/clk/tegra/clk.h
index 8724dc2..f94b178 100644
--- a/drivers/clk/tegra/clk.h
+++ b/drivers/clk/tegra/clk.h
@@ -202,6 +202,8 @@
* PLL's based on fractional divider value.
* @calc_rate: Callback used to change how out of table
* rates (dividers and multipler) are calculated.
+ * @adjust_vco: Callback to adjust the programming range of the
+ * divider range (if SDM is present)
*
* Flags:
* TEGRA_PLL_USE_LOCK - This flag indicated to use lock bits for
@@ -269,6 +271,8 @@
int (*calc_rate)(struct clk_hw *hw,
struct tegra_clk_pll_freq_table *cfg,
unsigned long rate, unsigned long parent_rate);
+ unsigned long (*adjust_vco)(struct tegra_clk_pll_params *pll_params,
+ unsigned long parent_rate);
};
#define TEGRA_PLL_USE_LOCK BIT(0)