| commit | b5ad2c21934951bbf6aadd8adbdd9889baad0ac0 | [log] [tgz] |
|---|---|---|
| author | Markos Chandras <markos.chandras@imgtec.com> | Thu Jan 15 10:28:29 2015 +0000 |
| committer | Markos Chandras <markos.chandras@imgtec.com> | Tue Feb 17 15:37:31 2015 +0000 |
| tree | 23c9d24715f1e3f8da4936f41fccb4217cb5a0d1 | |
| parent | 4ee486274ec1e63f056c991e2523c32780670d08 [diff] |
MIPS: mm: scache: Add secondary cache support for MIPS R6 cores The secondary cache initialization and configuration code is processor specific so we need to handle MIPS R6 cores as well. Signed-off-by: Markos Chandras <markos.chandras@imgtec.com>