ASoC: msm_sdw: Move the delay logic inside bulk write loop
On consecutive writes in bulk write API, ensure delay
is provided for atleast 100us between each soundwire
master write for WR_DONE status update and reflect
current register value. Also ensure delay in soundwire
master read is present after register address update
and before register value read.
CRs-Fixed: 2035787
Change-Id: I8399c5ca32328abdd4e90b46d6f8d6a6c0225905
Signed-off-by: Laxminath Kasam <lkasam@codeaurora.org>
diff --git a/sound/soc/codecs/msm_sdw/msm_sdw_cdc.c b/sound/soc/codecs/msm_sdw/msm_sdw_cdc.c
index 62fdb94..15d62c3 100644
--- a/sound/soc/codecs/msm_sdw/msm_sdw_cdc.c
+++ b/sound/soc/codecs/msm_sdw/msm_sdw_cdc.c
@@ -1039,7 +1039,6 @@
__func__, reg);
sdw_rd_addr_base = MSM_SDW_AHB_BRIDGE_RD_ADDR_0;
sdw_rd_data_base = MSM_SDW_AHB_BRIDGE_RD_DATA_0;
-
/*
* Add sleep as SWR slave access read takes time.
* Allow for RD_DONE to complete for previous register if any.
@@ -1054,6 +1053,8 @@
dev_err(msm_sdw->dev, "%s: RD Addr Failure\n", __func__);
goto err;
}
+ /* Add sleep for SWR register read value to get updated. */
+ usleep_range(100, 105);
/* Check for RD value */
ret = regmap_bulk_read(msm_sdw->regmap, sdw_rd_data_base,
(u8 *)&val, 4);
@@ -1079,12 +1080,12 @@
sdw_wr_addr_base = MSM_SDW_AHB_BRIDGE_WR_ADDR_0;
sdw_wr_data_base = MSM_SDW_AHB_BRIDGE_WR_DATA_0;
- /*
- * Add sleep as SWR slave write takes time.
- * Allow for any previous pending write to complete.
- */
- usleep_range(50, 55);
for (i = 0; i < len; i += 2) {
+ /*
+ * Add sleep as SWR slave write takes time.
+ * Allow for any previous pending write to complete.
+ */
+ usleep_range(100, 105);
/* First Write the Data to register */
ret = regmap_bulk_write(msm_sdw->regmap,
sdw_wr_data_base, bulk_reg[i].buf, 4);