tree 026a2f00b2876c43cc8287b7ffadf1e4061dc200
parent 1ce5bdb8312b6e9629029340063ea1e5cfac435d
parent 91bbc174d45c347aa7aedb2215cc7d2013c06c1f
author Linus Torvalds <torvalds@linux-foundation.org> 1477369819 -0700
committer Linus Torvalds <torvalds@linux-foundation.org> 1477369819 -0700
mergetag object 91bbc174d45c347aa7aedb2215cc7d2013c06c1f
 type commit
 tag clk-fixes-for-linus
 tagger Stephen Boyd <sboyd@codeaurora.org> 1477339882 -0700
 
 This is the first batch of clk driver fixes for this release. We have a handful
 of fixes for the uniphier clk driver that was introduced recently, as well as
 Kconfig option hiding, module autoloading markings, and a few fixes for clk_hw
 based registration patches that went in this merge window.
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Merge tag 'clk-fixes-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux

Pull clk fixes from Stephen Boyd:
 "This is the first batch of clk driver fixes for this release.

  We have a handful of fixes for the uniphier clk driver that was
  introduced recently, as well as Kconfig option hiding, module
  autoloading markings, and a few fixes for clk_hw based registration
  patches that went in this merge window"

* tag 'clk-fixes-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux:
  clk: at91: Fix a return value in case of error
  clk: uniphier: rename MIO clock to SD clock for Pro5, PXs2, LD20 SoCs
  clk: uniphier: fix memory overrun bug
  clk: hi6220: use CLK_OF_DECLARE_DRIVER for sysctrl and mediactrl clock init
  clk: mvebu: armada-37xx-periph: Fix the clock gate flag
  clk: bcm2835: Clamp the PLL's requested rate to the hardware limits.
  clk: max77686: fix number of clocks setup for clk_hw based registration
  clk: mvebu: armada-37xx-periph: Fix the clock provider registration
  clk: core: add __init decoration for CLK_OF_DECLARE_DRIVER function
  clk: mediatek: Add hardware dependency
  clk: samsung: clk-exynos-audss: Fix module autoload
  clk: uniphier: fix type of variable passed to regmap_read()
  clk: uniphier: add system clock support for sLD3 SoC