| commit | b7854efce20be7c7bcd43424dee027124e9af27f | [log] [tgz] |
|---|---|---|
| author | Jisheng Zhang <jszhang@marvell.com> | Wed Mar 30 19:53:41 2016 +0800 |
| committer | David S. Miller <davem@davemloft.net> | Thu Mar 31 15:15:01 2016 -0400 |
| tree | 575b50e44f64c2bb478199db773e15b7d376df20 | |
| parent | 13a7ebb38a659254e71a4a95cf39429a9287912b [diff] |
net: mvpp2: replace MVPP2_CPU_D_CACHE_LINE_SIZE with L1_CACHE_BYTES The mvpp2 ip maybe used in SoCs which may have have 64bytes cacheline size. Replace the MVPP2_CPU_D_CACHE_LINE_SIZE with L1_CACHE_BYTES. And since dma_alloc_coherent() is always cacheline size aligned, so remove the align checks. Signed-off-by: Jisheng Zhang <jszhang@marvell.com> Signed-off-by: David S. Miller <davem@davemloft.net>