tree a6fb82b4e251e429e8c193a2b5c95515c015dfc2
parent f0c71718c2968a744f834b26423b9fb5e7d41a34
author Julien CHAUVEAU <julien.chauveau@neo-technologies.fr> 1416562061 +0100
committer Heiko Stuebner <heiko@sntech.de> 1416699597 +0100

clk: rockchip: fix clock gate for rk3188 spdif_pre

In rk3188 clock branches, spdif_pre gate was set to RK2928_CLKGATE_CON(13) bit 13.
This appears to be a copy-paste error because such a register does not exist.
We correct it to RK2928_CLKGATE_CON(0) and find out that the rk3188 spdif clock
is the same as the rk3066 spdif clock, so we move it to the common clock branches.

Signed-off-by: Julien CHAUVEAU <julien.chauveau@neo-technologies.fr>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>