Merge tag 'topic/drm-misc-2015-06-22' of git://anongit.freedesktop.org/drm-intel into drm-next
One more drm-misc pull for 4.2. The important one is the fix from Laurent
for Daniel Stone's mode_blob work.
* tag 'topic/drm-misc-2015-06-22' of git://anongit.freedesktop.org/drm-intel:
drm/atomic: Don't set crtc_state->enable manually
drm: prime: Document gem_prime_mmap
drm: Avoid the double clflush on the last cache line in drm_clflush_virt_range()
drm/atomic: Extract needs_modeset function
drm/cma: Fix 64-bit size_t build warnings
Documentation/drm: Update rotation property
diff --git a/Documentation/devicetree/bindings/panel/hannstar,hsd100pxn1.txt b/Documentation/devicetree/bindings/panel/hannstar,hsd100pxn1.txt
new file mode 100644
index 0000000..8270319
--- /dev/null
+++ b/Documentation/devicetree/bindings/panel/hannstar,hsd100pxn1.txt
@@ -0,0 +1,7 @@
+HannStar Display Corp. HSD100PXN1 10.1" XGA LVDS panel
+
+Required properties:
+- compatible: should be "hannstar,hsd100pxn1"
+
+This binding is compatible with the simple-panel binding, which is specified
+in simple-panel.txt in this directory.
diff --git a/Documentation/devicetree/bindings/panel/lg,lb070wv8.txt b/Documentation/devicetree/bindings/panel/lg,lb070wv8.txt
new file mode 100644
index 0000000..a7588e5
--- /dev/null
+++ b/Documentation/devicetree/bindings/panel/lg,lb070wv8.txt
@@ -0,0 +1,7 @@
+LG 7" (800x480 pixels) TFT LCD panel
+
+Required properties:
+- compatible: should be "lg,lb070wv8"
+
+This binding is compatible with the simple-panel binding, which is specified
+in simple-panel.txt in this directory.
diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c b/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c
index 96c904b..c991973 100644
--- a/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c
+++ b/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c
@@ -553,7 +553,7 @@
/* Validate arguments */
if ((args->buf_size_in_bytes > MAX_ALLOWED_AW_BUFF_SIZE) ||
- (args->buf_size_in_bytes <= sizeof(*args)) ||
+ (args->buf_size_in_bytes <= sizeof(*args) + sizeof(int) * 2) ||
(cmd_from_user == NULL))
return -EINVAL;
@@ -590,7 +590,7 @@
/* skip over the addresses buffer */
args_idx += sizeof(aw_info.watch_address) * aw_info.num_watch_points;
- if (args_idx >= args->buf_size_in_bytes) {
+ if (args_idx >= args->buf_size_in_bytes - sizeof(*args)) {
kfree(args_buff);
return -EINVAL;
}
@@ -614,7 +614,7 @@
args_idx += sizeof(aw_info.watch_mask);
}
- if (args_idx > args->buf_size_in_bytes) {
+ if (args_idx >= args->buf_size_in_bytes - sizeof(args)) {
kfree(args_buff);
return -EINVAL;
}
diff --git a/drivers/gpu/drm/bridge/dw_hdmi.c b/drivers/gpu/drm/bridge/dw_hdmi.c
index 49cafb6..816d104 100644
--- a/drivers/gpu/drm/bridge/dw_hdmi.c
+++ b/drivers/gpu/drm/bridge/dw_hdmi.c
@@ -1395,7 +1395,7 @@
struct dw_hdmi *hdmi = container_of(connector, struct dw_hdmi,
connector);
struct edid *edid;
- int ret;
+ int ret = 0;
if (!hdmi->ddc)
return 0;
@@ -1412,7 +1412,7 @@
dev_dbg(hdmi->dev, "failed to get edid\n");
}
- return 0;
+ return ret;
}
static enum drm_mode_status
@@ -1457,7 +1457,7 @@
.best_encoder = dw_hdmi_connector_best_encoder,
};
-struct drm_bridge_funcs dw_hdmi_bridge_funcs = {
+static struct drm_bridge_funcs dw_hdmi_bridge_funcs = {
.enable = dw_hdmi_bridge_enable,
.disable = dw_hdmi_bridge_disable,
.pre_enable = dw_hdmi_bridge_nop,
diff --git a/drivers/gpu/drm/bridge/ps8622.c b/drivers/gpu/drm/bridge/ps8622.c
index e895aa7..32c4601 100644
--- a/drivers/gpu/drm/bridge/ps8622.c
+++ b/drivers/gpu/drm/bridge/ps8622.c
@@ -18,6 +18,7 @@
#include <linux/err.h>
#include <linux/fb.h>
#include <linux/gpio.h>
+#include <linux/gpio/consumer.h>
#include <linux/i2c.h>
#include <linux/module.h>
#include <linux/of.h>
@@ -581,31 +582,21 @@
ps8622->v12 = NULL;
}
- ps8622->gpio_slp = devm_gpiod_get(dev, "sleep");
+ ps8622->gpio_slp = devm_gpiod_get(dev, "sleep", GPIOD_OUT_HIGH);
if (IS_ERR(ps8622->gpio_slp)) {
ret = PTR_ERR(ps8622->gpio_slp);
dev_err(dev, "cannot get gpio_slp %d\n", ret);
return ret;
}
- ret = gpiod_direction_output(ps8622->gpio_slp, 1);
- if (ret) {
- dev_err(dev, "cannot configure gpio_slp\n");
- return ret;
- }
- ps8622->gpio_rst = devm_gpiod_get(dev, "reset");
- if (IS_ERR(ps8622->gpio_rst)) {
- ret = PTR_ERR(ps8622->gpio_rst);
- dev_err(dev, "cannot get gpio_rst %d\n", ret);
- return ret;
- }
/*
* Assert the reset pin high to avoid the bridge being
* initialized prematurely
*/
- ret = gpiod_direction_output(ps8622->gpio_rst, 1);
- if (ret) {
- dev_err(dev, "cannot configure gpio_rst\n");
+ ps8622->gpio_rst = devm_gpiod_get(dev, "reset", GPIOD_OUT_HIGH);
+ if (IS_ERR(ps8622->gpio_rst)) {
+ ret = PTR_ERR(ps8622->gpio_rst);
+ dev_err(dev, "cannot get gpio_rst %d\n", ret);
return ret;
}
diff --git a/drivers/gpu/drm/bridge/ptn3460.c b/drivers/gpu/drm/bridge/ptn3460.c
index 9d2f053..0e08156 100644
--- a/drivers/gpu/drm/bridge/ptn3460.c
+++ b/drivers/gpu/drm/bridge/ptn3460.c
@@ -15,6 +15,7 @@
#include <linux/delay.h>
#include <linux/gpio.h>
+#include <linux/gpio/consumer.h>
#include <linux/i2c.h>
#include <linux/module.h>
#include <linux/of.h>
@@ -23,8 +24,6 @@
#include <drm/drm_panel.h>
-#include "bridge/ptn3460.h"
-
#include "drm_crtc.h"
#include "drm_crtc_helper.h"
#include "drm_edid.h"
@@ -330,32 +329,23 @@
ptn_bridge->client = client;
- ptn_bridge->gpio_pd_n = devm_gpiod_get(&client->dev, "powerdown");
+ ptn_bridge->gpio_pd_n = devm_gpiod_get(&client->dev, "powerdown",
+ GPIOD_OUT_HIGH);
if (IS_ERR(ptn_bridge->gpio_pd_n)) {
ret = PTR_ERR(ptn_bridge->gpio_pd_n);
dev_err(dev, "cannot get gpio_pd_n %d\n", ret);
return ret;
}
- ret = gpiod_direction_output(ptn_bridge->gpio_pd_n, 1);
- if (ret) {
- DRM_ERROR("cannot configure gpio_pd_n\n");
- return ret;
- }
-
- ptn_bridge->gpio_rst_n = devm_gpiod_get(&client->dev, "reset");
- if (IS_ERR(ptn_bridge->gpio_rst_n)) {
- ret = PTR_ERR(ptn_bridge->gpio_rst_n);
- DRM_ERROR("cannot get gpio_rst_n %d\n", ret);
- return ret;
- }
/*
* Request the reset pin low to avoid the bridge being
* initialized prematurely
*/
- ret = gpiod_direction_output(ptn_bridge->gpio_rst_n, 0);
- if (ret) {
- DRM_ERROR("cannot configure gpio_rst_n\n");
+ ptn_bridge->gpio_rst_n = devm_gpiod_get(&client->dev, "reset",
+ GPIOD_OUT_LOW);
+ if (IS_ERR(ptn_bridge->gpio_rst_n)) {
+ ret = PTR_ERR(ptn_bridge->gpio_rst_n);
+ DRM_ERROR("cannot get gpio_rst_n %d\n", ret);
return ret;
}
@@ -389,7 +379,7 @@
}
static const struct i2c_device_id ptn3460_i2c_table[] = {
- {"nxp,ptn3460", 0},
+ {"ptn3460", 0},
{},
};
MODULE_DEVICE_TABLE(i2c, ptn3460_i2c_table);
diff --git a/drivers/gpu/drm/exynos/exynos_dp_core.c b/drivers/gpu/drm/exynos/exynos_dp_core.c
index 30feb7d..15b0865 100644
--- a/drivers/gpu/drm/exynos/exynos_dp_core.c
+++ b/drivers/gpu/drm/exynos/exynos_dp_core.c
@@ -29,7 +29,6 @@
#include <drm/drm_crtc.h>
#include <drm/drm_crtc_helper.h>
#include <drm/drm_panel.h>
-#include <drm/bridge/ptn3460.h>
#include "exynos_dp_core.h"
diff --git a/drivers/gpu/drm/i915/i915_cmd_parser.c b/drivers/gpu/drm/i915/i915_cmd_parser.c
index 9605ff8..306d9e4 100644
--- a/drivers/gpu/drm/i915/i915_cmd_parser.c
+++ b/drivers/gpu/drm/i915/i915_cmd_parser.c
@@ -123,7 +123,7 @@
CMD( MI_SEMAPHORE_MBOX, SMI, !F, 0xFF, R ),
CMD( MI_STORE_DWORD_INDEX, SMI, !F, 0xFF, R ),
CMD( MI_LOAD_REGISTER_IMM(1), SMI, !F, 0xFF, W,
- .reg = { .offset = 1, .mask = 0x007FFFFC } ),
+ .reg = { .offset = 1, .mask = 0x007FFFFC, .step = 2 } ),
CMD( MI_STORE_REGISTER_MEM(1), SMI, !F, 0xFF, W | B,
.reg = { .offset = 1, .mask = 0x007FFFFC },
.bits = {{
@@ -395,16 +395,38 @@
/*
* Register whitelists, sorted by increasing register offset.
+ */
+
+/*
+ * An individual whitelist entry granting access to register addr. If
+ * mask is non-zero the argument of immediate register writes will be
+ * AND-ed with mask, and the command will be rejected if the result
+ * doesn't match value.
+ *
+ * Registers with non-zero mask are only allowed to be written using
+ * LRI.
+ */
+struct drm_i915_reg_descriptor {
+ u32 addr;
+ u32 mask;
+ u32 value;
+};
+
+/* Convenience macro for adding 32-bit registers. */
+#define REG32(address, ...) \
+ { .addr = address, __VA_ARGS__ }
+
+/*
+ * Convenience macro for adding 64-bit registers.
*
* Some registers that userspace accesses are 64 bits. The register
* access commands only allow 32-bit accesses. Hence, we have to include
* entries for both halves of the 64-bit registers.
*/
+#define REG64(addr) \
+ REG32(addr), REG32(addr + sizeof(u32))
-/* Convenience macro for adding 64-bit registers */
-#define REG64(addr) (addr), (addr + sizeof(u32))
-
-static const u32 gen7_render_regs[] = {
+static const struct drm_i915_reg_descriptor gen7_render_regs[] = {
REG64(GPGPU_THREADS_DISPATCHED),
REG64(HS_INVOCATION_COUNT),
REG64(DS_INVOCATION_COUNT),
@@ -417,15 +439,15 @@
REG64(CL_PRIMITIVES_COUNT),
REG64(PS_INVOCATION_COUNT),
REG64(PS_DEPTH_COUNT),
- OACONTROL, /* Only allowed for LRI and SRM. See below. */
+ REG32(OACONTROL), /* Only allowed for LRI and SRM. See below. */
REG64(MI_PREDICATE_SRC0),
REG64(MI_PREDICATE_SRC1),
- GEN7_3DPRIM_END_OFFSET,
- GEN7_3DPRIM_START_VERTEX,
- GEN7_3DPRIM_VERTEX_COUNT,
- GEN7_3DPRIM_INSTANCE_COUNT,
- GEN7_3DPRIM_START_INSTANCE,
- GEN7_3DPRIM_BASE_VERTEX,
+ REG32(GEN7_3DPRIM_END_OFFSET),
+ REG32(GEN7_3DPRIM_START_VERTEX),
+ REG32(GEN7_3DPRIM_VERTEX_COUNT),
+ REG32(GEN7_3DPRIM_INSTANCE_COUNT),
+ REG32(GEN7_3DPRIM_START_INSTANCE),
+ REG32(GEN7_3DPRIM_BASE_VERTEX),
REG64(GEN7_SO_NUM_PRIMS_WRITTEN(0)),
REG64(GEN7_SO_NUM_PRIMS_WRITTEN(1)),
REG64(GEN7_SO_NUM_PRIMS_WRITTEN(2)),
@@ -434,33 +456,41 @@
REG64(GEN7_SO_PRIM_STORAGE_NEEDED(1)),
REG64(GEN7_SO_PRIM_STORAGE_NEEDED(2)),
REG64(GEN7_SO_PRIM_STORAGE_NEEDED(3)),
- GEN7_SO_WRITE_OFFSET(0),
- GEN7_SO_WRITE_OFFSET(1),
- GEN7_SO_WRITE_OFFSET(2),
- GEN7_SO_WRITE_OFFSET(3),
- GEN7_L3SQCREG1,
- GEN7_L3CNTLREG2,
- GEN7_L3CNTLREG3,
+ REG32(GEN7_SO_WRITE_OFFSET(0)),
+ REG32(GEN7_SO_WRITE_OFFSET(1)),
+ REG32(GEN7_SO_WRITE_OFFSET(2)),
+ REG32(GEN7_SO_WRITE_OFFSET(3)),
+ REG32(GEN7_L3SQCREG1),
+ REG32(GEN7_L3CNTLREG2),
+ REG32(GEN7_L3CNTLREG3),
+ REG32(HSW_SCRATCH1,
+ .mask = ~HSW_SCRATCH1_L3_DATA_ATOMICS_DISABLE,
+ .value = 0),
+ REG32(HSW_ROW_CHICKEN3,
+ .mask = ~(HSW_ROW_CHICKEN3_L3_GLOBAL_ATOMICS_DISABLE << 16 |
+ HSW_ROW_CHICKEN3_L3_GLOBAL_ATOMICS_DISABLE),
+ .value = 0),
};
-static const u32 gen7_blt_regs[] = {
- BCS_SWCTRL,
+static const struct drm_i915_reg_descriptor gen7_blt_regs[] = {
+ REG32(BCS_SWCTRL),
};
-static const u32 ivb_master_regs[] = {
- FORCEWAKE_MT,
- DERRMR,
- GEN7_PIPE_DE_LOAD_SL(PIPE_A),
- GEN7_PIPE_DE_LOAD_SL(PIPE_B),
- GEN7_PIPE_DE_LOAD_SL(PIPE_C),
+static const struct drm_i915_reg_descriptor ivb_master_regs[] = {
+ REG32(FORCEWAKE_MT),
+ REG32(DERRMR),
+ REG32(GEN7_PIPE_DE_LOAD_SL(PIPE_A)),
+ REG32(GEN7_PIPE_DE_LOAD_SL(PIPE_B)),
+ REG32(GEN7_PIPE_DE_LOAD_SL(PIPE_C)),
};
-static const u32 hsw_master_regs[] = {
- FORCEWAKE_MT,
- DERRMR,
+static const struct drm_i915_reg_descriptor hsw_master_regs[] = {
+ REG32(FORCEWAKE_MT),
+ REG32(DERRMR),
};
#undef REG64
+#undef REG32
static u32 gen7_render_get_cmd_length_mask(u32 cmd_header)
{
@@ -550,14 +580,16 @@
return ret;
}
-static bool check_sorted(int ring_id, const u32 *reg_table, int reg_count)
+static bool check_sorted(int ring_id,
+ const struct drm_i915_reg_descriptor *reg_table,
+ int reg_count)
{
int i;
u32 previous = 0;
bool ret = true;
for (i = 0; i < reg_count; i++) {
- u32 curr = reg_table[i];
+ u32 curr = reg_table[i].addr;
if (curr < previous) {
DRM_ERROR("CMD: table not sorted ring=%d entry=%d reg=0x%08X prev=0x%08X\n",
@@ -804,18 +836,20 @@
return default_desc;
}
-static bool valid_reg(const u32 *table, int count, u32 addr)
+static const struct drm_i915_reg_descriptor *
+find_reg(const struct drm_i915_reg_descriptor *table,
+ int count, u32 addr)
{
- if (table && count != 0) {
+ if (table) {
int i;
for (i = 0; i < count; i++) {
- if (table[i] == addr)
- return true;
+ if (table[i].addr == addr)
+ return &table[i];
}
}
- return false;
+ return NULL;
}
static u32 *vmap_batch(struct drm_i915_gem_object *obj,
@@ -934,7 +968,7 @@
static bool check_cmd(const struct intel_engine_cs *ring,
const struct drm_i915_cmd_descriptor *desc,
- const u32 *cmd,
+ const u32 *cmd, u32 length,
const bool is_master,
bool *oacontrol_set)
{
@@ -950,38 +984,70 @@
}
if (desc->flags & CMD_DESC_REGISTER) {
- u32 reg_addr = cmd[desc->reg.offset] & desc->reg.mask;
-
/*
- * OACONTROL requires some special handling for writes. We
- * want to make sure that any batch which enables OA also
- * disables it before the end of the batch. The goal is to
- * prevent one process from snooping on the perf data from
- * another process. To do that, we need to check the value
- * that will be written to the register. Hence, limit
- * OACONTROL writes to only MI_LOAD_REGISTER_IMM commands.
+ * Get the distance between individual register offset
+ * fields if the command can perform more than one
+ * access at a time.
*/
- if (reg_addr == OACONTROL) {
- if (desc->cmd.value == MI_LOAD_REGISTER_MEM) {
- DRM_DEBUG_DRIVER("CMD: Rejected LRM to OACONTROL\n");
+ const u32 step = desc->reg.step ? desc->reg.step : length;
+ u32 offset;
+
+ for (offset = desc->reg.offset; offset < length;
+ offset += step) {
+ const u32 reg_addr = cmd[offset] & desc->reg.mask;
+ const struct drm_i915_reg_descriptor *reg =
+ find_reg(ring->reg_table, ring->reg_count,
+ reg_addr);
+
+ if (!reg && is_master)
+ reg = find_reg(ring->master_reg_table,
+ ring->master_reg_count,
+ reg_addr);
+
+ if (!reg) {
+ DRM_DEBUG_DRIVER("CMD: Rejected register 0x%08X in command: 0x%08X (ring=%d)\n",
+ reg_addr, *cmd, ring->id);
return false;
}
- if (desc->cmd.value == MI_LOAD_REGISTER_IMM(1))
- *oacontrol_set = (cmd[2] != 0);
- }
+ /*
+ * OACONTROL requires some special handling for
+ * writes. We want to make sure that any batch which
+ * enables OA also disables it before the end of the
+ * batch. The goal is to prevent one process from
+ * snooping on the perf data from another process. To do
+ * that, we need to check the value that will be written
+ * to the register. Hence, limit OACONTROL writes to
+ * only MI_LOAD_REGISTER_IMM commands.
+ */
+ if (reg_addr == OACONTROL) {
+ if (desc->cmd.value == MI_LOAD_REGISTER_MEM) {
+ DRM_DEBUG_DRIVER("CMD: Rejected LRM to OACONTROL\n");
+ return false;
+ }
- if (!valid_reg(ring->reg_table,
- ring->reg_count, reg_addr)) {
- if (!is_master ||
- !valid_reg(ring->master_reg_table,
- ring->master_reg_count,
- reg_addr)) {
- DRM_DEBUG_DRIVER("CMD: Rejected register 0x%08X in command: 0x%08X (ring=%d)\n",
- reg_addr,
- *cmd,
- ring->id);
- return false;
+ if (desc->cmd.value == MI_LOAD_REGISTER_IMM(1))
+ *oacontrol_set = (cmd[offset + 1] != 0);
+ }
+
+ /*
+ * Check the value written to the register against the
+ * allowed mask/value pair given in the whitelist entry.
+ */
+ if (reg->mask) {
+ if (desc->cmd.value == MI_LOAD_REGISTER_MEM) {
+ DRM_DEBUG_DRIVER("CMD: Rejected LRM to masked register 0x%08X\n",
+ reg_addr);
+ return false;
+ }
+
+ if (desc->cmd.value == MI_LOAD_REGISTER_IMM(1) &&
+ (offset + 2 > length ||
+ (cmd[offset + 1] & reg->mask) != reg->value)) {
+ DRM_DEBUG_DRIVER("CMD: Rejected LRI to masked register 0x%08X\n",
+ reg_addr);
+ return false;
+ }
}
}
}
@@ -1105,7 +1171,8 @@
break;
}
- if (!check_cmd(ring, desc, cmd, is_master, &oacontrol_set)) {
+ if (!check_cmd(ring, desc, cmd, length, is_master,
+ &oacontrol_set)) {
ret = -EINVAL;
break;
}
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 72f5a3f..542fac6 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -2300,10 +2300,15 @@
* Describes where to find a register address in the command to check
* against the ring's register whitelist. Only valid if flags has the
* CMD_DESC_REGISTER bit set.
+ *
+ * A non-zero step value implies that the command may access multiple
+ * registers in sequence (e.g. LRI), in that case step gives the
+ * distance in dwords between individual offset fields.
*/
struct {
u32 offset;
u32 mask;
+ u32 step;
} reg;
#define MAX_CMD_DESC_BITMASKS 3
diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
index be35f04..c35e035 100644
--- a/drivers/gpu/drm/i915/i915_gem.c
+++ b/drivers/gpu/drm/i915/i915_gem.c
@@ -2813,9 +2813,6 @@
{
WARN_ON(i915_verify_lists(ring->dev));
- if (list_empty(&ring->active_list))
- return;
-
/* Retire requests first as we use it above for the early return.
* If we retire requests last, we may use a later seqno and so clear
* the requests lists without clearing the active list, leading to
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 4e3f302..e047105 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -87,7 +87,8 @@
struct intel_crtc_state *pipe_config);
static int intel_set_mode(struct drm_crtc *crtc,
- struct drm_atomic_state *state);
+ struct drm_atomic_state *state,
+ bool force_restore);
static int intel_framebuffer_init(struct drm_device *dev,
struct intel_framebuffer *ifb,
struct drm_mode_fb_cmd2 *mode_cmd,
@@ -10096,7 +10097,7 @@
drm_mode_copy(&crtc_state->base.mode, mode);
- if (intel_set_mode(crtc, state)) {
+ if (intel_set_mode(crtc, state, true)) {
DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n");
if (old->release_fb)
old->release_fb->funcs->destroy(old->release_fb);
@@ -10170,7 +10171,7 @@
if (ret)
goto fail;
- ret = intel_set_mode(crtc, state);
+ ret = intel_set_mode(crtc, state, true);
if (ret)
goto fail;
@@ -11385,10 +11386,6 @@
crtc->base.enabled = crtc->base.state->enable;
crtc->config = to_intel_crtc_state(crtc->base.state);
}
-
- /* Copy the new configuration to the staged state, to keep the few
- * pieces of code that haven't been converted yet happy */
- intel_modeset_update_staged_output_state(state->dev);
}
static void
@@ -12646,20 +12643,24 @@
}
static int intel_set_mode_with_config(struct drm_crtc *crtc,
- struct intel_crtc_state *pipe_config)
+ struct intel_crtc_state *pipe_config,
+ bool force_restore)
{
int ret;
ret = __intel_set_mode(crtc, pipe_config);
- if (ret == 0)
+ if (ret == 0 && force_restore) {
+ intel_modeset_update_staged_output_state(crtc->dev);
intel_modeset_check_state(crtc->dev);
+ }
return ret;
}
static int intel_set_mode(struct drm_crtc *crtc,
- struct drm_atomic_state *state)
+ struct drm_atomic_state *state,
+ bool force_restore)
{
struct intel_crtc_state *pipe_config;
int ret = 0;
@@ -12670,7 +12671,7 @@
goto out;
}
- ret = intel_set_mode_with_config(crtc, pipe_config);
+ ret = intel_set_mode_with_config(crtc, pipe_config, force_restore);
if (ret)
goto out;
@@ -12682,7 +12683,6 @@
{
struct drm_device *dev = crtc->dev;
struct drm_atomic_state *state;
- struct intel_crtc *intel_crtc;
struct intel_encoder *encoder;
struct intel_connector *connector;
struct drm_connector_state *connector_state;
@@ -12725,29 +12725,23 @@
}
}
- for_each_intel_crtc(dev, intel_crtc) {
- if (intel_crtc->new_enabled == intel_crtc->base.enabled)
- continue;
-
- crtc_state = intel_atomic_get_crtc_state(state, intel_crtc);
- if (IS_ERR(crtc_state)) {
- DRM_DEBUG_KMS("Failed to add [CRTC:%d] to state: %ld\n",
- intel_crtc->base.base.id,
- PTR_ERR(crtc_state));
- continue;
- }
-
- crtc_state->base.active = crtc_state->base.enable =
- intel_crtc->new_enabled;
-
- if (&intel_crtc->base == crtc)
- drm_mode_copy(&crtc_state->base.mode, &crtc->mode);
+ crtc_state = intel_atomic_get_crtc_state(state, to_intel_crtc(crtc));
+ if (IS_ERR(crtc_state)) {
+ DRM_DEBUG_KMS("Failed to add [CRTC:%d] to state: %ld\n",
+ crtc->base.id, PTR_ERR(crtc_state));
+ drm_atomic_state_free(state);
+ return;
}
+ crtc_state->base.active = crtc_state->base.enable =
+ to_intel_crtc(crtc)->new_enabled;
+
+ drm_mode_copy(&crtc_state->base.mode, &crtc->mode);
+
intel_modeset_setup_plane_state(state, crtc, &crtc->mode,
crtc->primary->fb, crtc->x, crtc->y);
- ret = intel_set_mode(crtc, state);
+ ret = intel_set_mode(crtc, state, false);
if (ret)
drm_atomic_state_free(state);
}
@@ -12947,7 +12941,7 @@
primary_plane_was_visible = primary_plane_visible(set->crtc);
- ret = intel_set_mode_with_config(set->crtc, pipe_config);
+ ret = intel_set_mode_with_config(set->crtc, pipe_config, true);
if (ret == 0 &&
pipe_config->base.enable &&
diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.h b/drivers/gpu/drm/i915/intel_ringbuffer.h
index 39f6dfc..e539314 100644
--- a/drivers/gpu/drm/i915/intel_ringbuffer.h
+++ b/drivers/gpu/drm/i915/intel_ringbuffer.h
@@ -118,6 +118,7 @@
};
struct intel_context;
+struct drm_i915_reg_descriptor;
struct intel_engine_cs {
const char *name;
@@ -300,14 +301,14 @@
/*
* Table of registers allowed in commands that read/write registers.
*/
- const u32 *reg_table;
+ const struct drm_i915_reg_descriptor *reg_table;
int reg_count;
/*
* Table of registers allowed in commands that read/write registers, but
* only from the DRM master.
*/
- const u32 *master_reg_table;
+ const struct drm_i915_reg_descriptor *master_reg_table;
int master_reg_count;
/*
diff --git a/drivers/gpu/drm/omapdrm/omap_connector.c b/drivers/gpu/drm/omapdrm/omap_connector.c
index 1773973..83f2a91 100644
--- a/drivers/gpu/drm/omapdrm/omap_connector.c
+++ b/drivers/gpu/drm/omapdrm/omap_connector.c
@@ -17,10 +17,11 @@
* this program. If not, see <http://www.gnu.org/licenses/>.
*/
-#include "omap_drv.h"
+#include <drm/drm_atomic_helper.h>
+#include <drm/drm_crtc.h>
+#include <drm/drm_crtc_helper.h>
-#include "drm_crtc.h"
-#include "drm_crtc_helper.h"
+#include "omap_drv.h"
/*
* connector funcs
@@ -259,10 +260,13 @@
}
static const struct drm_connector_funcs omap_connector_funcs = {
- .dpms = drm_helper_connector_dpms,
+ .dpms = drm_atomic_helper_connector_dpms,
+ .reset = drm_atomic_helper_connector_reset,
.detect = omap_connector_detect,
.fill_modes = drm_helper_probe_single_connector_modes,
.destroy = omap_connector_destroy,
+ .atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state,
+ .atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
};
static const struct drm_connector_helper_funcs omap_connector_helper_funcs = {
diff --git a/drivers/gpu/drm/omapdrm/omap_crtc.c b/drivers/gpu/drm/omapdrm/omap_crtc.c
index f456544..23d9c92 100644
--- a/drivers/gpu/drm/omapdrm/omap_crtc.c
+++ b/drivers/gpu/drm/omapdrm/omap_crtc.c
@@ -17,12 +17,14 @@
* this program. If not, see <http://www.gnu.org/licenses/>.
*/
-#include "omap_drv.h"
-
+#include <drm/drm_atomic.h>
+#include <drm/drm_atomic_helper.h>
+#include <drm/drm_crtc.h>
+#include <drm/drm_crtc_helper.h>
#include <drm/drm_mode.h>
#include <drm/drm_plane_helper.h>
-#include "drm_crtc.h"
-#include "drm_crtc_helper.h"
+
+#include "omap_drv.h"
#define to_omap_crtc(x) container_of(x, struct omap_crtc, base)
@@ -30,10 +32,7 @@
struct drm_crtc base;
const char *name;
- int pipe;
enum omap_channel channel;
- struct omap_overlay_manager_info info;
- struct drm_encoder *current_encoder;
/*
* Temporary: eventually this will go away, but it is needed
@@ -44,36 +43,14 @@
struct omap_overlay_manager *mgr;
struct omap_video_timings timings;
- bool enabled;
- struct omap_drm_apply apply;
-
- struct omap_drm_irq apply_irq;
+ struct omap_drm_irq vblank_irq;
struct omap_drm_irq error_irq;
- /* list of in-progress apply's: */
- struct list_head pending_applies;
-
- /* list of queued apply's: */
- struct list_head queued_applies;
-
- /* for handling queued and in-progress applies: */
- struct work_struct apply_work;
-
- /* if there is a pending flip, these will be non-null: */
- struct drm_pending_vblank_event *event;
- struct drm_framebuffer *old_fb;
-
- /* for handling page flips without caring about what
- * the callback is called from. Possibly we should just
- * make omap_gem always call the cb from the worker so
- * we don't have to care about this..
- *
- * XXX maybe fold into apply_work??
- */
- struct work_struct page_flip_work;
-
bool ignore_digit_sync_lost;
+
+ bool pending;
+ wait_queue_head_t pending_wait;
};
/* -----------------------------------------------------------------------------
@@ -87,7 +64,7 @@
return dispc_mgr_get_vsync_irq(omap_crtc->channel);
}
-const struct omap_video_timings *omap_crtc_timings(struct drm_crtc *crtc)
+struct omap_video_timings *omap_crtc_timings(struct drm_crtc *crtc)
{
struct omap_crtc *omap_crtc = to_omap_crtc(crtc);
return &omap_crtc->timings;
@@ -99,6 +76,15 @@
return omap_crtc->channel;
}
+int omap_crtc_wait_pending(struct drm_crtc *crtc)
+{
+ struct omap_crtc *omap_crtc = to_omap_crtc(crtc);
+
+ return wait_event_timeout(omap_crtc->pending_wait,
+ !omap_crtc->pending,
+ msecs_to_jiffies(50));
+}
+
/* -----------------------------------------------------------------------------
* DSS Manager Functions
*/
@@ -116,7 +102,7 @@
static struct omap_crtc *omap_crtcs[8];
/* we can probably ignore these until we support command-mode panels: */
-static int omap_crtc_connect(struct omap_overlay_manager *mgr,
+static int omap_crtc_dss_connect(struct omap_overlay_manager *mgr,
struct omap_dss_device *dst)
{
if (mgr->output)
@@ -131,18 +117,18 @@
return 0;
}
-static void omap_crtc_disconnect(struct omap_overlay_manager *mgr,
+static void omap_crtc_dss_disconnect(struct omap_overlay_manager *mgr,
struct omap_dss_device *dst)
{
mgr->output->manager = NULL;
mgr->output = NULL;
}
-static void omap_crtc_start_update(struct omap_overlay_manager *mgr)
+static void omap_crtc_dss_start_update(struct omap_overlay_manager *mgr)
{
}
-/* Called only from CRTC pre_apply and suspend/resume handlers. */
+/* Called only from the encoder enable/disable and suspend/resume handlers. */
static void omap_crtc_set_enabled(struct drm_crtc *crtc, bool enable)
{
struct drm_device *dev = crtc->dev;
@@ -200,11 +186,18 @@
}
-static int omap_crtc_enable(struct omap_overlay_manager *mgr)
+static int omap_crtc_dss_enable(struct omap_overlay_manager *mgr)
{
struct omap_crtc *omap_crtc = omap_crtcs[mgr->id];
+ struct omap_overlay_manager_info info;
- dispc_mgr_setup(omap_crtc->channel, &omap_crtc->info);
+ memset(&info, 0, sizeof(info));
+ info.default_color = 0x00000000;
+ info.trans_key = 0x00000000;
+ info.trans_key_type = OMAP_DSS_COLOR_KEY_GFX_DST;
+ info.trans_enabled = false;
+
+ dispc_mgr_setup(omap_crtc->channel, &info);
dispc_mgr_set_timings(omap_crtc->channel,
&omap_crtc->timings);
omap_crtc_set_enabled(&omap_crtc->base, true);
@@ -212,14 +205,14 @@
return 0;
}
-static void omap_crtc_disable(struct omap_overlay_manager *mgr)
+static void omap_crtc_dss_disable(struct omap_overlay_manager *mgr)
{
struct omap_crtc *omap_crtc = omap_crtcs[mgr->id];
omap_crtc_set_enabled(&omap_crtc->base, false);
}
-static void omap_crtc_set_timings(struct omap_overlay_manager *mgr,
+static void omap_crtc_dss_set_timings(struct omap_overlay_manager *mgr,
const struct omap_video_timings *timings)
{
struct omap_crtc *omap_crtc = omap_crtcs[mgr->id];
@@ -227,7 +220,7 @@
omap_crtc->timings = *timings;
}
-static void omap_crtc_set_lcd_config(struct omap_overlay_manager *mgr,
+static void omap_crtc_dss_set_lcd_config(struct omap_overlay_manager *mgr,
const struct dss_lcd_mgr_config *config)
{
struct omap_crtc *omap_crtc = omap_crtcs[mgr->id];
@@ -235,35 +228,62 @@
dispc_mgr_set_lcd_config(omap_crtc->channel, config);
}
-static int omap_crtc_register_framedone_handler(
+static int omap_crtc_dss_register_framedone(
struct omap_overlay_manager *mgr,
void (*handler)(void *), void *data)
{
return 0;
}
-static void omap_crtc_unregister_framedone_handler(
+static void omap_crtc_dss_unregister_framedone(
struct omap_overlay_manager *mgr,
void (*handler)(void *), void *data)
{
}
static const struct dss_mgr_ops mgr_ops = {
- .connect = omap_crtc_connect,
- .disconnect = omap_crtc_disconnect,
- .start_update = omap_crtc_start_update,
- .enable = omap_crtc_enable,
- .disable = omap_crtc_disable,
- .set_timings = omap_crtc_set_timings,
- .set_lcd_config = omap_crtc_set_lcd_config,
- .register_framedone_handler = omap_crtc_register_framedone_handler,
- .unregister_framedone_handler = omap_crtc_unregister_framedone_handler,
+ .connect = omap_crtc_dss_connect,
+ .disconnect = omap_crtc_dss_disconnect,
+ .start_update = omap_crtc_dss_start_update,
+ .enable = omap_crtc_dss_enable,
+ .disable = omap_crtc_dss_disable,
+ .set_timings = omap_crtc_dss_set_timings,
+ .set_lcd_config = omap_crtc_dss_set_lcd_config,
+ .register_framedone_handler = omap_crtc_dss_register_framedone,
+ .unregister_framedone_handler = omap_crtc_dss_unregister_framedone,
};
/* -----------------------------------------------------------------------------
- * Apply Logic
+ * Setup, Flush and Page Flip
*/
+static void omap_crtc_complete_page_flip(struct drm_crtc *crtc)
+{
+ struct drm_pending_vblank_event *event;
+ struct drm_device *dev = crtc->dev;
+ unsigned long flags;
+
+ event = crtc->state->event;
+
+ if (!event)
+ return;
+
+ spin_lock_irqsave(&dev->event_lock, flags);
+
+ list_del(&event->base.link);
+
+ /*
+ * Queue the event for delivery if it's still linked to a file
+ * handle, otherwise just destroy it.
+ */
+ if (event->base.file_priv)
+ drm_crtc_send_vblank_event(crtc, event);
+ else
+ event->base.destroy(&event->base);
+
+ spin_unlock_irqrestore(&dev->event_lock, flags);
+}
+
static void omap_crtc_error_irq(struct omap_drm_irq *irq, uint32_t irqstatus)
{
struct omap_crtc *omap_crtc =
@@ -278,168 +298,29 @@
DRM_ERROR_RATELIMITED("%s: errors: %08x\n", omap_crtc->name, irqstatus);
}
-static void omap_crtc_apply_irq(struct omap_drm_irq *irq, uint32_t irqstatus)
+static void omap_crtc_vblank_irq(struct omap_drm_irq *irq, uint32_t irqstatus)
{
struct omap_crtc *omap_crtc =
- container_of(irq, struct omap_crtc, apply_irq);
- struct drm_crtc *crtc = &omap_crtc->base;
+ container_of(irq, struct omap_crtc, vblank_irq);
+ struct drm_device *dev = omap_crtc->base.dev;
- if (!dispc_mgr_go_busy(omap_crtc->channel)) {
- struct omap_drm_private *priv =
- crtc->dev->dev_private;
- DBG("%s: apply done", omap_crtc->name);
- __omap_irq_unregister(crtc->dev, &omap_crtc->apply_irq);
- queue_work(priv->wq, &omap_crtc->apply_work);
- }
-}
+ if (dispc_mgr_go_busy(omap_crtc->channel))
+ return;
-static void apply_worker(struct work_struct *work)
-{
- struct omap_crtc *omap_crtc =
- container_of(work, struct omap_crtc, apply_work);
- struct drm_crtc *crtc = &omap_crtc->base;
- struct drm_device *dev = crtc->dev;
- struct omap_drm_apply *apply, *n;
- bool need_apply;
+ DBG("%s: apply done", omap_crtc->name);
- /*
- * Synchronize everything on mode_config.mutex, to keep
- * the callbacks and list modification all serialized
- * with respect to modesetting ioctls from userspace.
- */
- drm_modeset_lock(&crtc->mutex, NULL);
- dispc_runtime_get();
+ __omap_irq_unregister(dev, &omap_crtc->vblank_irq);
- /*
- * If we are still pending a previous update, wait.. when the
- * pending update completes, we get kicked again.
- */
- if (omap_crtc->apply_irq.registered)
- goto out;
+ rmb();
+ WARN_ON(!omap_crtc->pending);
+ omap_crtc->pending = false;
+ wmb();
- /* finish up previous apply's: */
- list_for_each_entry_safe(apply, n,
- &omap_crtc->pending_applies, pending_node) {
- apply->post_apply(apply);
- list_del(&apply->pending_node);
- }
+ /* wake up userspace */
+ omap_crtc_complete_page_flip(&omap_crtc->base);
- need_apply = !list_empty(&omap_crtc->queued_applies);
-
- /* then handle the next round of of queued apply's: */
- list_for_each_entry_safe(apply, n,
- &omap_crtc->queued_applies, queued_node) {
- apply->pre_apply(apply);
- list_del(&apply->queued_node);
- apply->queued = false;
- list_add_tail(&apply->pending_node,
- &omap_crtc->pending_applies);
- }
-
- if (need_apply) {
- enum omap_channel channel = omap_crtc->channel;
-
- DBG("%s: GO", omap_crtc->name);
-
- if (dispc_mgr_is_enabled(channel)) {
- dispc_mgr_go(channel);
- omap_irq_register(dev, &omap_crtc->apply_irq);
- } else {
- struct omap_drm_private *priv = dev->dev_private;
- queue_work(priv->wq, &omap_crtc->apply_work);
- }
- }
-
-out:
- dispc_runtime_put();
- drm_modeset_unlock(&crtc->mutex);
-}
-
-int omap_crtc_apply(struct drm_crtc *crtc,
- struct omap_drm_apply *apply)
-{
- struct omap_crtc *omap_crtc = to_omap_crtc(crtc);
-
- WARN_ON(!drm_modeset_is_locked(&crtc->mutex));
-
- /* no need to queue it again if it is already queued: */
- if (apply->queued)
- return 0;
-
- apply->queued = true;
- list_add_tail(&apply->queued_node, &omap_crtc->queued_applies);
-
- /*
- * If there are no currently pending updates, then go ahead and
- * kick the worker immediately, otherwise it will run again when
- * the current update finishes.
- */
- if (list_empty(&omap_crtc->pending_applies)) {
- struct omap_drm_private *priv = crtc->dev->dev_private;
- queue_work(priv->wq, &omap_crtc->apply_work);
- }
-
- return 0;
-}
-
-static void omap_crtc_pre_apply(struct omap_drm_apply *apply)
-{
- struct omap_crtc *omap_crtc =
- container_of(apply, struct omap_crtc, apply);
- struct drm_crtc *crtc = &omap_crtc->base;
- struct omap_drm_private *priv = crtc->dev->dev_private;
- struct drm_encoder *encoder = NULL;
- unsigned int i;
-
- DBG("%s: enabled=%d", omap_crtc->name, omap_crtc->enabled);
-
- for (i = 0; i < priv->num_encoders; i++) {
- if (priv->encoders[i]->crtc == crtc) {
- encoder = priv->encoders[i];
- break;
- }
- }
-
- if (omap_crtc->current_encoder && encoder != omap_crtc->current_encoder)
- omap_encoder_set_enabled(omap_crtc->current_encoder, false);
-
- omap_crtc->current_encoder = encoder;
-
- if (!omap_crtc->enabled) {
- if (encoder)
- omap_encoder_set_enabled(encoder, false);
- } else {
- if (encoder) {
- omap_encoder_set_enabled(encoder, false);
- omap_encoder_update(encoder, omap_crtc->mgr,
- &omap_crtc->timings);
- omap_encoder_set_enabled(encoder, true);
- }
- }
-}
-
-static void omap_crtc_post_apply(struct omap_drm_apply *apply)
-{
- /* nothing needed for post-apply */
-}
-
-void omap_crtc_flush(struct drm_crtc *crtc)
-{
- struct omap_crtc *omap_crtc = to_omap_crtc(crtc);
- int loops = 0;
-
- while (!list_empty(&omap_crtc->pending_applies) ||
- !list_empty(&omap_crtc->queued_applies) ||
- omap_crtc->event || omap_crtc->old_fb) {
-
- if (++loops > 10) {
- dev_err(crtc->dev->dev,
- "omap_crtc_flush() timeout\n");
- break;
- }
-
- schedule_timeout_uninterruptible(msecs_to_jiffies(20));
- }
+ /* wake up omap_atomic_complete */
+ wake_up(&omap_crtc->pending_wait);
}
/* -----------------------------------------------------------------------------
@@ -452,7 +333,7 @@
DBG("%s", omap_crtc->name);
- WARN_ON(omap_crtc->apply_irq.registered);
+ WARN_ON(omap_crtc->vblank_irq.registered);
omap_irq_unregister(crtc->dev, &omap_crtc->error_irq);
drm_crtc_cleanup(crtc);
@@ -460,28 +341,6 @@
kfree(omap_crtc);
}
-static void omap_crtc_dpms(struct drm_crtc *crtc, int mode)
-{
- struct omap_drm_private *priv = crtc->dev->dev_private;
- struct omap_crtc *omap_crtc = to_omap_crtc(crtc);
- bool enabled = (mode == DRM_MODE_DPMS_ON);
- int i;
-
- DBG("%s: %d", omap_crtc->name, mode);
-
- if (enabled != omap_crtc->enabled) {
- omap_crtc->enabled = enabled;
- omap_crtc_apply(crtc, &omap_crtc->apply);
-
- /* Enable/disable all planes associated with the CRTC. */
- for (i = 0; i < priv->num_planes; i++) {
- struct drm_plane *plane = priv->planes[i];
- if (plane->crtc == crtc)
- WARN_ON(omap_plane_set_enable(plane, enabled));
- }
- }
-}
-
static bool omap_crtc_mode_fixup(struct drm_crtc *crtc,
const struct drm_display_mode *mode,
struct drm_display_mode *adjusted_mode)
@@ -489,187 +348,127 @@
return true;
}
-static int omap_crtc_mode_set(struct drm_crtc *crtc,
- struct drm_display_mode *mode,
- struct drm_display_mode *adjusted_mode,
- int x, int y,
- struct drm_framebuffer *old_fb)
+static void omap_crtc_enable(struct drm_crtc *crtc)
{
struct omap_crtc *omap_crtc = to_omap_crtc(crtc);
- mode = adjusted_mode;
+ DBG("%s", omap_crtc->name);
+
+ rmb();
+ WARN_ON(omap_crtc->pending);
+ omap_crtc->pending = true;
+ wmb();
+
+ omap_irq_register(crtc->dev, &omap_crtc->vblank_irq);
+
+ drm_crtc_vblank_on(crtc);
+}
+
+static void omap_crtc_disable(struct drm_crtc *crtc)
+{
+ struct omap_crtc *omap_crtc = to_omap_crtc(crtc);
+
+ DBG("%s", omap_crtc->name);
+
+ drm_crtc_vblank_off(crtc);
+}
+
+static void omap_crtc_mode_set_nofb(struct drm_crtc *crtc)
+{
+ struct omap_crtc *omap_crtc = to_omap_crtc(crtc);
+ struct drm_display_mode *mode = &crtc->state->adjusted_mode;
DBG("%s: set mode: %d:\"%s\" %d %d %d %d %d %d %d %d %d %d 0x%x 0x%x",
- omap_crtc->name, mode->base.id, mode->name,
- mode->vrefresh, mode->clock,
- mode->hdisplay, mode->hsync_start,
- mode->hsync_end, mode->htotal,
- mode->vdisplay, mode->vsync_start,
- mode->vsync_end, mode->vtotal,
- mode->type, mode->flags);
+ omap_crtc->name, mode->base.id, mode->name,
+ mode->vrefresh, mode->clock,
+ mode->hdisplay, mode->hsync_start, mode->hsync_end, mode->htotal,
+ mode->vdisplay, mode->vsync_start, mode->vsync_end, mode->vtotal,
+ mode->type, mode->flags);
copy_timings_drm_to_omap(&omap_crtc->timings, mode);
-
- /*
- * The primary plane CRTC can be reset if the plane is disabled directly
- * through the universal plane API. Set it again here.
- */
- crtc->primary->crtc = crtc;
-
- return omap_plane_mode_set(crtc->primary, crtc, crtc->primary->fb,
- 0, 0, mode->hdisplay, mode->vdisplay,
- x, y, mode->hdisplay, mode->vdisplay,
- NULL, NULL);
}
-static void omap_crtc_prepare(struct drm_crtc *crtc)
+static void omap_crtc_atomic_begin(struct drm_crtc *crtc)
+{
+}
+
+static void omap_crtc_atomic_flush(struct drm_crtc *crtc)
{
struct omap_crtc *omap_crtc = to_omap_crtc(crtc);
- DBG("%s", omap_crtc->name);
- omap_crtc_dpms(crtc, DRM_MODE_DPMS_OFF);
+
+ WARN_ON(omap_crtc->vblank_irq.registered);
+
+ if (dispc_mgr_is_enabled(omap_crtc->channel)) {
+
+ DBG("%s: GO", omap_crtc->name);
+
+ rmb();
+ WARN_ON(omap_crtc->pending);
+ omap_crtc->pending = true;
+ wmb();
+
+ dispc_mgr_go(omap_crtc->channel);
+ omap_irq_register(crtc->dev, &omap_crtc->vblank_irq);
+ }
+
+ crtc->invert_dimensions = !!(crtc->primary->state->rotation &
+ (BIT(DRM_ROTATE_90) | BIT(DRM_ROTATE_270)));
}
-static void omap_crtc_commit(struct drm_crtc *crtc)
+static int omap_crtc_atomic_set_property(struct drm_crtc *crtc,
+ struct drm_crtc_state *state,
+ struct drm_property *property,
+ uint64_t val)
{
- struct omap_crtc *omap_crtc = to_omap_crtc(crtc);
- DBG("%s", omap_crtc->name);
- omap_crtc_dpms(crtc, DRM_MODE_DPMS_ON);
-}
-
-static int omap_crtc_mode_set_base(struct drm_crtc *crtc, int x, int y,
- struct drm_framebuffer *old_fb)
-{
+ struct drm_plane_state *plane_state;
struct drm_plane *plane = crtc->primary;
- struct drm_display_mode *mode = &crtc->mode;
-
- return omap_plane_mode_set(plane, crtc, crtc->primary->fb,
- 0, 0, mode->hdisplay, mode->vdisplay,
- x, y, mode->hdisplay, mode->vdisplay,
- NULL, NULL);
-}
-
-static void vblank_cb(void *arg)
-{
- struct drm_crtc *crtc = arg;
- struct drm_device *dev = crtc->dev;
- struct omap_crtc *omap_crtc = to_omap_crtc(crtc);
- unsigned long flags;
- struct drm_framebuffer *fb;
-
- spin_lock_irqsave(&dev->event_lock, flags);
-
- /* wakeup userspace */
- if (omap_crtc->event)
- drm_send_vblank_event(dev, omap_crtc->pipe, omap_crtc->event);
-
- fb = omap_crtc->old_fb;
-
- omap_crtc->event = NULL;
- omap_crtc->old_fb = NULL;
-
- spin_unlock_irqrestore(&dev->event_lock, flags);
-
- if (fb)
- drm_framebuffer_unreference(fb);
-}
-
-static void page_flip_worker(struct work_struct *work)
-{
- struct omap_crtc *omap_crtc =
- container_of(work, struct omap_crtc, page_flip_work);
- struct drm_crtc *crtc = &omap_crtc->base;
- struct drm_display_mode *mode = &crtc->mode;
- struct drm_gem_object *bo;
-
- drm_modeset_lock(&crtc->mutex, NULL);
- omap_plane_mode_set(crtc->primary, crtc, crtc->primary->fb,
- 0, 0, mode->hdisplay, mode->vdisplay,
- crtc->x, crtc->y, mode->hdisplay, mode->vdisplay,
- vblank_cb, crtc);
- drm_modeset_unlock(&crtc->mutex);
-
- bo = omap_framebuffer_bo(crtc->primary->fb, 0);
- drm_gem_object_unreference_unlocked(bo);
-}
-
-static void page_flip_cb(void *arg)
-{
- struct drm_crtc *crtc = arg;
- struct omap_crtc *omap_crtc = to_omap_crtc(crtc);
- struct omap_drm_private *priv = crtc->dev->dev_private;
-
- /* avoid assumptions about what ctxt we are called from: */
- queue_work(priv->wq, &omap_crtc->page_flip_work);
-}
-
-static int omap_crtc_page_flip_locked(struct drm_crtc *crtc,
- struct drm_framebuffer *fb,
- struct drm_pending_vblank_event *event,
- uint32_t page_flip_flags)
-{
- struct drm_device *dev = crtc->dev;
- struct omap_crtc *omap_crtc = to_omap_crtc(crtc);
- struct drm_plane *primary = crtc->primary;
- struct drm_gem_object *bo;
- unsigned long flags;
-
- DBG("%d -> %d (event=%p)", primary->fb ? primary->fb->base.id : -1,
- fb->base.id, event);
-
- spin_lock_irqsave(&dev->event_lock, flags);
-
- if (omap_crtc->old_fb) {
- spin_unlock_irqrestore(&dev->event_lock, flags);
- dev_err(dev->dev, "already a pending flip\n");
- return -EBUSY;
- }
-
- omap_crtc->event = event;
- omap_crtc->old_fb = primary->fb = fb;
- drm_framebuffer_reference(omap_crtc->old_fb);
-
- spin_unlock_irqrestore(&dev->event_lock, flags);
/*
- * Hold a reference temporarily until the crtc is updated
- * and takes the reference to the bo. This avoids it
- * getting freed from under us:
+ * Delegate property set to the primary plane. Get the plane state and
+ * set the property directly.
*/
- bo = omap_framebuffer_bo(fb, 0);
- drm_gem_object_reference(bo);
- omap_gem_op_async(bo, OMAP_GEM_READ, page_flip_cb, crtc);
+ plane_state = drm_atomic_get_plane_state(state->state, plane);
+ if (!plane_state)
+ return -EINVAL;
- return 0;
+ return drm_atomic_plane_set_property(plane, plane_state, property, val);
}
-static int omap_crtc_set_property(struct drm_crtc *crtc,
- struct drm_property *property, uint64_t val)
+static int omap_crtc_atomic_get_property(struct drm_crtc *crtc,
+ const struct drm_crtc_state *state,
+ struct drm_property *property,
+ uint64_t *val)
{
- struct omap_drm_private *priv = crtc->dev->dev_private;
-
- if (property == priv->rotation_prop) {
- crtc->invert_dimensions =
- !!(val & ((1LL << DRM_ROTATE_90) | (1LL << DRM_ROTATE_270)));
- }
-
- return omap_plane_set_property(crtc->primary, property, val);
+ /*
+ * Delegate property get to the primary plane. The
+ * drm_atomic_plane_get_property() function isn't exported, but can be
+ * called through drm_object_property_get_value() as that will call
+ * drm_atomic_get_property() for atomic drivers.
+ */
+ return drm_object_property_get_value(&crtc->primary->base, property,
+ val);
}
static const struct drm_crtc_funcs omap_crtc_funcs = {
- .set_config = drm_crtc_helper_set_config,
+ .reset = drm_atomic_helper_crtc_reset,
+ .set_config = drm_atomic_helper_set_config,
.destroy = omap_crtc_destroy,
- .page_flip = omap_crtc_page_flip_locked,
- .set_property = omap_crtc_set_property,
+ .page_flip = drm_atomic_helper_page_flip,
+ .set_property = drm_atomic_helper_crtc_set_property,
+ .atomic_duplicate_state = drm_atomic_helper_crtc_duplicate_state,
+ .atomic_destroy_state = drm_atomic_helper_crtc_destroy_state,
+ .atomic_set_property = omap_crtc_atomic_set_property,
+ .atomic_get_property = omap_crtc_atomic_get_property,
};
static const struct drm_crtc_helper_funcs omap_crtc_helper_funcs = {
- .dpms = omap_crtc_dpms,
.mode_fixup = omap_crtc_mode_fixup,
- .mode_set = omap_crtc_mode_set,
- .prepare = omap_crtc_prepare,
- .commit = omap_crtc_commit,
- .mode_set_base = omap_crtc_mode_set_base,
+ .mode_set_nofb = omap_crtc_mode_set_nofb,
+ .disable = omap_crtc_disable,
+ .enable = omap_crtc_enable,
+ .atomic_begin = omap_crtc_atomic_begin,
+ .atomic_flush = omap_crtc_atomic_flush,
};
/* -----------------------------------------------------------------------------
@@ -699,7 +498,6 @@
{
struct drm_crtc *crtc = NULL;
struct omap_crtc *omap_crtc;
- struct omap_overlay_manager_info *info;
int ret;
DBG("%s", channel_names[channel]);
@@ -710,21 +508,13 @@
crtc = &omap_crtc->base;
- INIT_WORK(&omap_crtc->page_flip_work, page_flip_worker);
- INIT_WORK(&omap_crtc->apply_work, apply_worker);
-
- INIT_LIST_HEAD(&omap_crtc->pending_applies);
- INIT_LIST_HEAD(&omap_crtc->queued_applies);
-
- omap_crtc->apply.pre_apply = omap_crtc_pre_apply;
- omap_crtc->apply.post_apply = omap_crtc_post_apply;
+ init_waitqueue_head(&omap_crtc->pending_wait);
omap_crtc->channel = channel;
omap_crtc->name = channel_names[channel];
- omap_crtc->pipe = id;
- omap_crtc->apply_irq.irqmask = pipe2vbl(crtc);
- omap_crtc->apply_irq.irq = omap_crtc_apply_irq;
+ omap_crtc->vblank_irq.irqmask = pipe2vbl(crtc);
+ omap_crtc->vblank_irq.irq = omap_crtc_vblank_irq;
omap_crtc->error_irq.irqmask =
dispc_mgr_get_sync_lost_irq(channel);
@@ -734,13 +524,6 @@
/* temporary: */
omap_crtc->mgr = omap_dss_get_overlay_manager(channel);
- /* TODO: fix hard-coded setup.. add properties! */
- info = &omap_crtc->info;
- info->default_color = 0x00000000;
- info->trans_key = 0x00000000;
- info->trans_key_type = OMAP_DSS_COLOR_KEY_GFX_DST;
- info->trans_enabled = false;
-
ret = drm_crtc_init_with_planes(dev, crtc, plane, NULL,
&omap_crtc_funcs);
if (ret < 0) {
diff --git a/drivers/gpu/drm/omapdrm/omap_debugfs.c b/drivers/gpu/drm/omapdrm/omap_debugfs.c
index d4c04d6..ee91a25 100644
--- a/drivers/gpu/drm/omapdrm/omap_debugfs.c
+++ b/drivers/gpu/drm/omapdrm/omap_debugfs.c
@@ -17,12 +17,12 @@
* this program. If not, see <http://www.gnu.org/licenses/>.
*/
+#include <drm/drm_crtc.h>
+#include <drm/drm_fb_helper.h>
+
#include "omap_drv.h"
#include "omap_dmm_tiler.h"
-#include "drm_fb_helper.h"
-
-
#ifdef CONFIG_DEBUG_FS
static int gem_show(struct seq_file *m, void *arg)
diff --git a/drivers/gpu/drm/omapdrm/omap_dmm_tiler.c b/drivers/gpu/drm/omapdrm/omap_dmm_tiler.c
index 042038e..f2daad8 100644
--- a/drivers/gpu/drm/omapdrm/omap_dmm_tiler.c
+++ b/drivers/gpu/drm/omapdrm/omap_dmm_tiler.c
@@ -15,21 +15,22 @@
* of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
+
+#include <linux/completion.h>
+#include <linux/delay.h>
+#include <linux/dma-mapping.h>
+#include <linux/errno.h>
#include <linux/init.h>
+#include <linux/interrupt.h>
+#include <linux/list.h>
+#include <linux/mm.h>
#include <linux/module.h>
#include <linux/platform_device.h> /* platform_device() */
-#include <linux/errno.h>
#include <linux/sched.h>
-#include <linux/wait.h>
-#include <linux/interrupt.h>
-#include <linux/dma-mapping.h>
#include <linux/slab.h>
-#include <linux/vmalloc.h>
-#include <linux/delay.h>
-#include <linux/mm.h>
#include <linux/time.h>
-#include <linux/list.h>
-#include <linux/completion.h>
+#include <linux/vmalloc.h>
+#include <linux/wait.h>
#include "omap_dmm_tiler.h"
#include "omap_dmm_priv.h"
diff --git a/drivers/gpu/drm/omapdrm/omap_drv.c b/drivers/gpu/drm/omapdrm/omap_drv.c
index 94920d4..419c2e4 100644
--- a/drivers/gpu/drm/omapdrm/omap_drv.c
+++ b/drivers/gpu/drm/omapdrm/omap_drv.c
@@ -17,11 +17,15 @@
* this program. If not, see <http://www.gnu.org/licenses/>.
*/
-#include "omap_drv.h"
+#include <linux/wait.h>
-#include "drm_crtc_helper.h"
-#include "drm_fb_helper.h"
+#include <drm/drm_atomic.h>
+#include <drm/drm_atomic_helper.h>
+#include <drm/drm_crtc_helper.h>
+#include <drm/drm_fb_helper.h>
+
#include "omap_dmm_tiler.h"
+#include "omap_drv.h"
#define DRIVER_NAME MODULE_NAME
#define DRIVER_DESC "OMAP DRM"
@@ -55,9 +59,153 @@
drm_fb_helper_hotplug_event(priv->fbdev);
}
+struct omap_atomic_state_commit {
+ struct work_struct work;
+ struct drm_device *dev;
+ struct drm_atomic_state *state;
+ u32 crtcs;
+};
+
+static void omap_atomic_wait_for_completion(struct drm_device *dev,
+ struct drm_atomic_state *old_state)
+{
+ struct drm_crtc_state *old_crtc_state;
+ struct drm_crtc *crtc;
+ unsigned int i;
+ int ret;
+
+ for_each_crtc_in_state(old_state, crtc, old_crtc_state, i) {
+ if (!crtc->state->enable)
+ continue;
+
+ ret = omap_crtc_wait_pending(crtc);
+
+ if (!ret)
+ dev_warn(dev->dev,
+ "atomic complete timeout (pipe %u)!\n", i);
+ }
+}
+
+static void omap_atomic_complete(struct omap_atomic_state_commit *commit)
+{
+ struct drm_device *dev = commit->dev;
+ struct omap_drm_private *priv = dev->dev_private;
+ struct drm_atomic_state *old_state = commit->state;
+
+ /* Apply the atomic update. */
+ dispc_runtime_get();
+
+ drm_atomic_helper_commit_modeset_disables(dev, old_state);
+ drm_atomic_helper_commit_planes(dev, old_state);
+ drm_atomic_helper_commit_modeset_enables(dev, old_state);
+
+ omap_atomic_wait_for_completion(dev, old_state);
+
+ drm_atomic_helper_cleanup_planes(dev, old_state);
+
+ dispc_runtime_put();
+
+ drm_atomic_state_free(old_state);
+
+ /* Complete the commit, wake up any waiter. */
+ spin_lock(&priv->commit.lock);
+ priv->commit.pending &= ~commit->crtcs;
+ spin_unlock(&priv->commit.lock);
+
+ wake_up_all(&priv->commit.wait);
+
+ kfree(commit);
+}
+
+static void omap_atomic_work(struct work_struct *work)
+{
+ struct omap_atomic_state_commit *commit =
+ container_of(work, struct omap_atomic_state_commit, work);
+
+ omap_atomic_complete(commit);
+}
+
+static bool omap_atomic_is_pending(struct omap_drm_private *priv,
+ struct omap_atomic_state_commit *commit)
+{
+ bool pending;
+
+ spin_lock(&priv->commit.lock);
+ pending = priv->commit.pending & commit->crtcs;
+ spin_unlock(&priv->commit.lock);
+
+ return pending;
+}
+
+static int omap_atomic_commit(struct drm_device *dev,
+ struct drm_atomic_state *state, bool async)
+{
+ struct omap_drm_private *priv = dev->dev_private;
+ struct omap_atomic_state_commit *commit;
+ unsigned long flags;
+ unsigned int i;
+ int ret;
+
+ ret = drm_atomic_helper_prepare_planes(dev, state);
+ if (ret)
+ return ret;
+
+ /* Allocate the commit object. */
+ commit = kzalloc(sizeof(*commit), GFP_KERNEL);
+ if (commit == NULL) {
+ ret = -ENOMEM;
+ goto error;
+ }
+
+ INIT_WORK(&commit->work, omap_atomic_work);
+ commit->dev = dev;
+ commit->state = state;
+
+ /* Wait until all affected CRTCs have completed previous commits and
+ * mark them as pending.
+ */
+ for (i = 0; i < dev->mode_config.num_crtc; ++i) {
+ if (state->crtcs[i])
+ commit->crtcs |= 1 << drm_crtc_index(state->crtcs[i]);
+ }
+
+ wait_event(priv->commit.wait, !omap_atomic_is_pending(priv, commit));
+
+ spin_lock(&priv->commit.lock);
+ priv->commit.pending |= commit->crtcs;
+ spin_unlock(&priv->commit.lock);
+
+ /* Keep track of all CRTC events to unlink them in preclose(). */
+ spin_lock_irqsave(&dev->event_lock, flags);
+ for (i = 0; i < dev->mode_config.num_crtc; ++i) {
+ struct drm_crtc_state *cstate = state->crtc_states[i];
+
+ if (cstate && cstate->event)
+ list_add_tail(&cstate->event->base.link,
+ &priv->commit.events);
+ }
+ spin_unlock_irqrestore(&dev->event_lock, flags);
+
+ /* Swap the state, this is the point of no return. */
+ drm_atomic_helper_swap_state(dev, state);
+
+ if (async)
+ schedule_work(&commit->work);
+ else
+ omap_atomic_complete(commit);
+
+ return 0;
+
+error:
+ drm_atomic_helper_cleanup_planes(dev, state);
+ return ret;
+}
+
static const struct drm_mode_config_funcs omap_mode_config_funcs = {
.fb_create = omap_framebuffer_create,
.output_poll_changed = omap_fb_output_poll_changed,
+ .atomic_check = drm_atomic_helper_check,
+ .atomic_commit = omap_atomic_commit,
};
static int get_connector_type(struct omap_dss_device *dssdev)
@@ -151,6 +299,27 @@
return 0;
}
+static int omap_modeset_init_properties(struct drm_device *dev)
+{
+ struct omap_drm_private *priv = dev->dev_private;
+
+ if (priv->has_dmm) {
+ dev->mode_config.rotation_property =
+ drm_mode_create_rotation_property(dev,
+ BIT(DRM_ROTATE_0) | BIT(DRM_ROTATE_90) |
+ BIT(DRM_ROTATE_180) | BIT(DRM_ROTATE_270) |
+ BIT(DRM_REFLECT_X) | BIT(DRM_REFLECT_Y));
+ if (!dev->mode_config.rotation_property)
+ return -ENOMEM;
+ }
+
+ priv->zorder_prop = drm_property_create_range(dev, 0, "zorder", 0, 3);
+ if (!priv->zorder_prop)
+ return -ENOMEM;
+
+ return 0;
+}
+
static int omap_modeset_init(struct drm_device *dev)
{
struct omap_drm_private *priv = dev->dev_private;
@@ -165,6 +334,10 @@
omap_drm_irq_install(dev);
+ ret = omap_modeset_init_properties(dev);
+ if (ret < 0)
+ return ret;
+
/*
* We usually don't want to create a CRTC for each manager, at least
* not until we have a way to expose private planes to userspace.
@@ -325,6 +498,8 @@
dev->mode_config.funcs = &omap_mode_config_funcs;
+ drm_mode_config_reset(dev);
+
return 0;
}
@@ -477,6 +652,7 @@
{
struct omap_drm_platform_data *pdata = dev->dev->platform_data;
struct omap_drm_private *priv;
+ unsigned int i;
int ret;
DBG("load: dev=%p", dev);
@@ -490,6 +666,9 @@
dev->dev_private = priv;
priv->wq = alloc_ordered_workqueue("omapdrm", 0);
+ init_waitqueue_head(&priv->commit.wait);
+ spin_lock_init(&priv->commit.lock);
+ INIT_LIST_HEAD(&priv->commit.events);
spin_lock_init(&priv->list_lock);
INIT_LIST_HEAD(&priv->obj_list);
@@ -504,10 +683,14 @@
return ret;
}
+ /* Initialize vblank handling, start with all CRTCs disabled. */
ret = drm_vblank_init(dev, priv->num_crtcs);
if (ret)
dev_warn(dev->dev, "could not init vblank\n");
+ for (i = 0; i < priv->num_crtcs; i++)
+ drm_crtc_vblank_off(priv->crtcs[i]);
+
priv->fbdev = omap_fbdev_init(dev);
if (!priv->fbdev) {
dev_warn(dev->dev, "omap_fbdev_init failed\n");
@@ -525,7 +708,6 @@
static int dev_unload(struct drm_device *dev)
{
struct omap_drm_private *priv = dev->dev_private;
- int i;
DBG("unload: dev=%p", dev);
@@ -534,10 +716,6 @@
if (priv->fbdev)
omap_fbdev_free(dev);
- /* flush crtcs so the fbs get released */
- for (i = 0; i < priv->num_crtcs; i++)
- omap_crtc_flush(priv->crtcs[i]);
-
omap_modeset_free(dev);
omap_gem_deinit(dev);
@@ -583,7 +761,7 @@
DBG("lastclose: dev=%p", dev);
- if (priv->rotation_prop) {
+ if (dev->mode_config.rotation_property) {
/* need to restore default rotation state.. not sure
* if there is a cleaner way to restore properties to
* default state? Maybe a flag that properties should
@@ -592,12 +770,12 @@
*/
for (i = 0; i < priv->num_crtcs; i++) {
drm_object_property_set_value(&priv->crtcs[i]->base,
- priv->rotation_prop, 0);
+ dev->mode_config.rotation_property, 0);
}
for (i = 0; i < priv->num_planes; i++) {
drm_object_property_set_value(&priv->planes[i]->base,
- priv->rotation_prop, 0);
+ dev->mode_config.rotation_property, 0);
}
}
@@ -610,7 +788,24 @@
static void dev_preclose(struct drm_device *dev, struct drm_file *file)
{
+ struct omap_drm_private *priv = dev->dev_private;
+ struct drm_pending_event *event;
+ unsigned long flags;
+
DBG("preclose: dev=%p", dev);
+
+ /*
+ * Unlink all pending CRTC events to make sure they won't be queued up
+ * by a pending asynchronous commit.
+ */
+ spin_lock_irqsave(&dev->event_lock, flags);
+ list_for_each_entry(event, &priv->commit.events, link) {
+ if (event->file_priv == file) {
+ file->event_space += event->event->length;
+ event->file_priv = NULL;
+ }
+ }
+ spin_unlock_irqrestore(&dev->event_lock, flags);
}
static void dev_postclose(struct drm_device *dev, struct drm_file *file)
@@ -636,8 +831,7 @@
};
static struct drm_driver omap_drm_driver = {
- .driver_features = DRIVER_HAVE_IRQ | DRIVER_MODESET | DRIVER_GEM
- | DRIVER_PRIME,
+ .driver_features = DRIVER_MODESET | DRIVER_GEM | DRIVER_PRIME,
.load = dev_load,
.unload = dev_unload,
.open = dev_open,
@@ -648,10 +842,6 @@
.get_vblank_counter = drm_vblank_count,
.enable_vblank = omap_irq_enable_vblank,
.disable_vblank = omap_irq_disable_vblank,
- .irq_preinstall = omap_irq_preinstall,
- .irq_postinstall = omap_irq_postinstall,
- .irq_uninstall = omap_irq_uninstall,
- .irq_handler = omap_irq_handler,
#ifdef CONFIG_DEBUG_FS
.debugfs_init = omap_debugfs_init,
.debugfs_cleanup = omap_debugfs_cleanup,
diff --git a/drivers/gpu/drm/omapdrm/omap_drv.h b/drivers/gpu/drm/omapdrm/omap_drv.h
index b31c79f..ae2df41 100644
--- a/drivers/gpu/drm/omapdrm/omap_drv.h
+++ b/drivers/gpu/drm/omapdrm/omap_drv.h
@@ -20,15 +20,16 @@
#ifndef __OMAP_DRV_H__
#define __OMAP_DRV_H__
-#include <video/omapdss.h>
#include <linux/module.h>
+#include <linux/platform_data/omap_drm.h>
#include <linux/types.h>
+#include <linux/wait.h>
+#include <video/omapdss.h>
+
#include <drm/drmP.h>
#include <drm/drm_crtc_helper.h>
-#include <drm/omap_drm.h>
#include <drm/drm_gem.h>
-#include <linux/platform_data/omap_drm.h>
-
+#include <drm/omap_drm.h>
#define DBG(fmt, ...) DRM_DEBUG(fmt"\n", ##__VA_ARGS__)
#define VERB(fmt, ...) if (0) DRM_DEBUG(fmt, ##__VA_ARGS__) /* verbose debug */
@@ -50,21 +51,6 @@
uint32_t src_w, src_h;
};
-/* Once GO bit is set, we can't make further updates to shadowed registers
- * until the GO bit is cleared. So various parts in the kms code that need
- * to update shadowed registers queue up a pair of callbacks, pre_apply
- * which is called before setting GO bit, and post_apply that is called
- * after GO bit is cleared. The crtc manages the queuing, and everyone
- * else goes thru omap_crtc_apply() using these callbacks so that the
- * code which has to deal w/ GO bit state is centralized.
- */
-struct omap_drm_apply {
- struct list_head pending_node, queued_node;
- bool queued;
- void (*pre_apply)(struct omap_drm_apply *apply);
- void (*post_apply)(struct omap_drm_apply *apply);
-};
-
/* For transiently registering for different DSS irqs that various parts
* of the KMS code need during setup/configuration. We these are not
* necessarily the same as what drm_vblank_get/put() are requesting, and
@@ -114,13 +100,20 @@
bool has_dmm;
/* properties: */
- struct drm_property *rotation_prop;
struct drm_property *zorder_prop;
/* irq handling: */
struct list_head irq_list; /* list of omap_drm_irq */
uint32_t vblank_mask; /* irq bits set for userspace vblank */
struct omap_drm_irq error_handler;
+
+ /* atomic commit */
+ struct {
+ struct list_head events;
+ wait_queue_head_t wait;
+ u32 pending;
+ spinlock_t lock; /* Protects commit.pending */
+ } commit;
};
@@ -138,51 +131,31 @@
int omap_irq_enable_vblank(struct drm_device *dev, int crtc_id);
void omap_irq_disable_vblank(struct drm_device *dev, int crtc_id);
-irqreturn_t omap_irq_handler(int irq, void *arg);
-void omap_irq_preinstall(struct drm_device *dev);
-int omap_irq_postinstall(struct drm_device *dev);
-void omap_irq_uninstall(struct drm_device *dev);
void __omap_irq_register(struct drm_device *dev, struct omap_drm_irq *irq);
void __omap_irq_unregister(struct drm_device *dev, struct omap_drm_irq *irq);
void omap_irq_register(struct drm_device *dev, struct omap_drm_irq *irq);
void omap_irq_unregister(struct drm_device *dev, struct omap_drm_irq *irq);
-int omap_drm_irq_uninstall(struct drm_device *dev);
+void omap_drm_irq_uninstall(struct drm_device *dev);
int omap_drm_irq_install(struct drm_device *dev);
struct drm_fb_helper *omap_fbdev_init(struct drm_device *dev);
void omap_fbdev_free(struct drm_device *dev);
-const struct omap_video_timings *omap_crtc_timings(struct drm_crtc *crtc);
+struct omap_video_timings *omap_crtc_timings(struct drm_crtc *crtc);
enum omap_channel omap_crtc_channel(struct drm_crtc *crtc);
-int omap_crtc_apply(struct drm_crtc *crtc,
- struct omap_drm_apply *apply);
void omap_crtc_pre_init(void);
void omap_crtc_pre_uninit(void);
struct drm_crtc *omap_crtc_init(struct drm_device *dev,
struct drm_plane *plane, enum omap_channel channel, int id);
-void omap_crtc_flush(struct drm_crtc *crtc);
+int omap_crtc_wait_pending(struct drm_crtc *crtc);
struct drm_plane *omap_plane_init(struct drm_device *dev,
int id, enum drm_plane_type type);
-int omap_plane_set_enable(struct drm_plane *plane, bool enable);
-int omap_plane_mode_set(struct drm_plane *plane,
- struct drm_crtc *crtc, struct drm_framebuffer *fb,
- int crtc_x, int crtc_y,
- unsigned int crtc_w, unsigned int crtc_h,
- unsigned int src_x, unsigned int src_y,
- unsigned int src_w, unsigned int src_h,
- void (*fxn)(void *), void *arg);
void omap_plane_install_properties(struct drm_plane *plane,
struct drm_mode_object *obj);
-int omap_plane_set_property(struct drm_plane *plane,
- struct drm_property *property, uint64_t val);
struct drm_encoder *omap_encoder_init(struct drm_device *dev,
struct omap_dss_device *dssdev);
-int omap_encoder_set_enabled(struct drm_encoder *encoder, bool enabled);
-int omap_encoder_update(struct drm_encoder *encoder,
- struct omap_overlay_manager *mgr,
- struct omap_video_timings *timings);
struct drm_connector *omap_connector_init(struct drm_device *dev,
int connector_type, struct omap_dss_device *dssdev,
diff --git a/drivers/gpu/drm/omapdrm/omap_encoder.c b/drivers/gpu/drm/omapdrm/omap_encoder.c
index 7445fb1..7d9b32a 100644
--- a/drivers/gpu/drm/omapdrm/omap_encoder.c
+++ b/drivers/gpu/drm/omapdrm/omap_encoder.c
@@ -17,16 +17,14 @@
* this program. If not, see <http://www.gnu.org/licenses/>.
*/
+#include <linux/list.h>
+
+#include <drm/drm_crtc.h>
+#include <drm/drm_crtc_helper.h>
#include <drm/drm_edid.h>
#include "omap_drv.h"
-#include "drm_crtc.h"
-#include "drm_crtc_helper.h"
-
-#include <linux/list.h>
-
-
/*
* encoder funcs
*/
@@ -54,8 +52,6 @@
{
struct omap_encoder *omap_encoder = to_omap_encoder(encoder);
- omap_encoder_set_enabled(encoder, false);
-
drm_encoder_cleanup(encoder);
kfree(omap_encoder);
}
@@ -64,29 +60,6 @@
.destroy = omap_encoder_destroy,
};
-/*
- * The CRTC drm_crtc_helper_set_mode() doesn't really give us the right
- * order.. the easiest way to work around this for now is to make all
- * the encoder-helper's no-op's and have the omap_crtc code take care
- * of the sequencing and call us in the right points.
- *
- * Eventually to handle connecting CRTCs to different encoders properly,
- * either the CRTC helpers need to change or we need to replace
- * drm_crtc_helper_set_mode(), but lets wait until atomic-modeset for
- * that.
- */
-
-static void omap_encoder_dpms(struct drm_encoder *encoder, int mode)
-{
-}
-
-static bool omap_encoder_mode_fixup(struct drm_encoder *encoder,
- const struct drm_display_mode *mode,
- struct drm_display_mode *adjusted_mode)
-{
- return true;
-}
-
static void omap_encoder_mode_set(struct drm_encoder *encoder,
struct drm_display_mode *mode,
struct drm_display_mode *adjusted_mode)
@@ -118,44 +91,18 @@
}
}
-static void omap_encoder_prepare(struct drm_encoder *encoder)
-{
-}
-
-static void omap_encoder_commit(struct drm_encoder *encoder)
-{
-}
-
-static const struct drm_encoder_helper_funcs omap_encoder_helper_funcs = {
- .dpms = omap_encoder_dpms,
- .mode_fixup = omap_encoder_mode_fixup,
- .mode_set = omap_encoder_mode_set,
- .prepare = omap_encoder_prepare,
- .commit = omap_encoder_commit,
-};
-
-/*
- * Instead of relying on the helpers for modeset, the omap_crtc code
- * calls these functions in the proper sequence.
- */
-
-int omap_encoder_set_enabled(struct drm_encoder *encoder, bool enabled)
+static void omap_encoder_disable(struct drm_encoder *encoder)
{
struct omap_encoder *omap_encoder = to_omap_encoder(encoder);
struct omap_dss_device *dssdev = omap_encoder->dssdev;
struct omap_dss_driver *dssdrv = dssdev->driver;
- if (enabled) {
- return dssdrv->enable(dssdev);
- } else {
- dssdrv->disable(dssdev);
- return 0;
- }
+ dssdrv->disable(dssdev);
}
-int omap_encoder_update(struct drm_encoder *encoder,
- struct omap_overlay_manager *mgr,
- struct omap_video_timings *timings)
+static int omap_encoder_update(struct drm_encoder *encoder,
+ enum omap_channel channel,
+ struct omap_video_timings *timings)
{
struct drm_device *dev = encoder->dev;
struct omap_encoder *omap_encoder = to_omap_encoder(encoder);
@@ -163,7 +110,7 @@
struct omap_dss_driver *dssdrv = dssdev->driver;
int ret;
- dssdev->src->manager = mgr;
+ dssdev->src->manager = omap_dss_get_overlay_manager(channel);
if (dssdrv->check_timings) {
ret = dssdrv->check_timings(dssdev, timings);
@@ -189,6 +136,32 @@
return 0;
}
+static void omap_encoder_enable(struct drm_encoder *encoder)
+{
+ struct omap_encoder *omap_encoder = to_omap_encoder(encoder);
+ struct omap_dss_device *dssdev = omap_encoder->dssdev;
+ struct omap_dss_driver *dssdrv = dssdev->driver;
+
+ omap_encoder_update(encoder, omap_crtc_channel(encoder->crtc),
+ omap_crtc_timings(encoder->crtc));
+
+ dssdrv->enable(dssdev);
+}
+
+static int omap_encoder_atomic_check(struct drm_encoder *encoder,
+ struct drm_crtc_state *crtc_state,
+ struct drm_connector_state *conn_state)
+{
+ return 0;
+}
+
+static const struct drm_encoder_helper_funcs omap_encoder_helper_funcs = {
+ .mode_set = omap_encoder_mode_set,
+ .disable = omap_encoder_disable,
+ .enable = omap_encoder_enable,
+ .atomic_check = omap_encoder_atomic_check,
+};
+
/* initialize encoder */
struct drm_encoder *omap_encoder_init(struct drm_device *dev,
struct omap_dss_device *dssdev)
diff --git a/drivers/gpu/drm/omapdrm/omap_fb.c b/drivers/gpu/drm/omapdrm/omap_fb.c
index b2c1a29..0b967e7 100644
--- a/drivers/gpu/drm/omapdrm/omap_fb.c
+++ b/drivers/gpu/drm/omapdrm/omap_fb.c
@@ -17,11 +17,11 @@
* this program. If not, see <http://www.gnu.org/licenses/>.
*/
-#include "omap_drv.h"
-#include "omap_dmm_tiler.h"
+#include <drm/drm_crtc.h>
+#include <drm/drm_crtc_helper.h>
-#include "drm_crtc.h"
-#include "drm_crtc_helper.h"
+#include "omap_dmm_tiler.h"
+#include "omap_drv.h"
/*
* framebuffer funcs
@@ -89,6 +89,8 @@
int pin_count;
const struct format *format;
struct plane planes[4];
+ /* lock for pinning (pin_count and planes.paddr) */
+ struct mutex lock;
};
static int omap_framebuffer_create_handle(struct drm_framebuffer *fb,
@@ -250,8 +252,11 @@
struct omap_framebuffer *omap_fb = to_omap_framebuffer(fb);
int ret, i, n = drm_format_num_planes(fb->pixel_format);
+ mutex_lock(&omap_fb->lock);
+
if (omap_fb->pin_count > 0) {
omap_fb->pin_count++;
+ mutex_unlock(&omap_fb->lock);
return 0;
}
@@ -265,6 +270,8 @@
omap_fb->pin_count++;
+ mutex_unlock(&omap_fb->lock);
+
return 0;
fail:
@@ -274,6 +281,8 @@
plane->paddr = 0;
}
+ mutex_unlock(&omap_fb->lock);
+
return ret;
}
@@ -283,10 +292,14 @@
struct omap_framebuffer *omap_fb = to_omap_framebuffer(fb);
int ret, i, n = drm_format_num_planes(fb->pixel_format);
+ mutex_lock(&omap_fb->lock);
+
omap_fb->pin_count--;
- if (omap_fb->pin_count > 0)
+ if (omap_fb->pin_count > 0) {
+ mutex_unlock(&omap_fb->lock);
return 0;
+ }
for (i = 0; i < n; i++) {
struct plane *plane = &omap_fb->planes[i];
@@ -296,9 +309,12 @@
plane->paddr = 0;
}
+ mutex_unlock(&omap_fb->lock);
+
return 0;
fail:
+ mutex_unlock(&omap_fb->lock);
return ret;
}
@@ -411,6 +427,7 @@
fb = &omap_fb->base;
omap_fb->format = format;
+ mutex_init(&omap_fb->lock);
for (i = 0; i < n; i++) {
struct plane *plane = &omap_fb->planes[i];
diff --git a/drivers/gpu/drm/omapdrm/omap_fbdev.c b/drivers/gpu/drm/omapdrm/omap_fbdev.c
index 950cd33..23b5a84 100644
--- a/drivers/gpu/drm/omapdrm/omap_fbdev.c
+++ b/drivers/gpu/drm/omapdrm/omap_fbdev.c
@@ -17,10 +17,10 @@
* this program. If not, see <http://www.gnu.org/licenses/>.
*/
-#include "omap_drv.h"
+#include <drm/drm_crtc.h>
+#include <drm/drm_fb_helper.h>
-#include "drm_crtc.h"
-#include "drm_fb_helper.h"
+#include "omap_drv.h"
MODULE_PARM_DESC(ywrap, "Enable ywrap scrolling (omap44xx and later, default 'y')");
static bool ywrap_enabled = true;
diff --git a/drivers/gpu/drm/omapdrm/omap_gem.c b/drivers/gpu/drm/omapdrm/omap_gem.c
index e9718b9..2ab7780 100644
--- a/drivers/gpu/drm/omapdrm/omap_gem.c
+++ b/drivers/gpu/drm/omapdrm/omap_gem.c
@@ -17,9 +17,9 @@
* this program. If not, see <http://www.gnu.org/licenses/>.
*/
-
-#include <linux/spinlock.h>
#include <linux/shmem_fs.h>
+#include <linux/spinlock.h>
+
#include <drm/drm_vma_manager.h>
#include "omap_drv.h"
diff --git a/drivers/gpu/drm/omapdrm/omap_gem_dmabuf.c b/drivers/gpu/drm/omapdrm/omap_gem_dmabuf.c
index 344fd78..0cc71c9 100644
--- a/drivers/gpu/drm/omapdrm/omap_gem_dmabuf.c
+++ b/drivers/gpu/drm/omapdrm/omap_gem_dmabuf.c
@@ -17,10 +17,10 @@
* this program. If not, see <http://www.gnu.org/licenses/>.
*/
-#include "omap_drv.h"
-
#include <linux/dma-buf.h>
+#include "omap_drv.h"
+
static struct sg_table *omap_gem_map_dma_buf(
struct dma_buf_attachment *attachment,
enum dma_data_direction dir)
diff --git a/drivers/gpu/drm/omapdrm/omap_irq.c b/drivers/gpu/drm/omapdrm/omap_irq.c
index 3eb097e..249c0330 100644
--- a/drivers/gpu/drm/omapdrm/omap_irq.c
+++ b/drivers/gpu/drm/omapdrm/omap_irq.c
@@ -152,12 +152,10 @@
DBG("dev=%p, crtc=%d", dev, crtc_id);
- dispc_runtime_get();
spin_lock_irqsave(&list_lock, flags);
priv->vblank_mask |= pipe2vbl(crtc);
omap_irq_update(dev);
spin_unlock_irqrestore(&list_lock, flags);
- dispc_runtime_put();
return 0;
}
@@ -179,15 +177,13 @@
DBG("dev=%p, crtc=%d", dev, crtc_id);
- dispc_runtime_get();
spin_lock_irqsave(&list_lock, flags);
priv->vblank_mask &= ~pipe2vbl(crtc);
omap_irq_update(dev);
spin_unlock_irqrestore(&list_lock, flags);
- dispc_runtime_put();
}
-irqreturn_t omap_irq_handler(int irq, void *arg)
+static irqreturn_t omap_irq_handler(int irq, void *arg)
{
struct drm_device *dev = (struct drm_device *) arg;
struct omap_drm_private *priv = dev->dev_private;
@@ -222,23 +218,29 @@
return IRQ_HANDLED;
}
-void omap_irq_preinstall(struct drm_device *dev)
-{
- DBG("dev=%p", dev);
- dispc_runtime_get();
- dispc_clear_irqstatus(0xffffffff);
- dispc_runtime_put();
-}
+/*
+ * We need a special version, instead of just using drm_irq_install(),
+ * because we need to register the irq via omapdss. Once omapdss and
+ * omapdrm are merged together we can assign the dispc hwmod data to
+ * ourselves and drop these and just use drm_irq_{install,uninstall}()
+ */
-int omap_irq_postinstall(struct drm_device *dev)
+int omap_drm_irq_install(struct drm_device *dev)
{
struct omap_drm_private *priv = dev->dev_private;
struct omap_drm_irq *error_handler = &priv->error_handler;
-
- DBG("dev=%p", dev);
+ int ret;
INIT_LIST_HEAD(&priv->irq_list);
+ dispc_runtime_get();
+ dispc_clear_irqstatus(0xffffffff);
+ dispc_runtime_put();
+
+ ret = dispc_request_irq(omap_irq_handler, dev);
+ if (ret < 0)
+ return ret;
+
error_handler->irq = omap_irq_error_handler;
error_handler->irqmask = DISPC_IRQ_OCP_ERR;
@@ -249,76 +251,22 @@
omap_irq_register(dev, error_handler);
+ dev->irq_enabled = true;
+
return 0;
}
-void omap_irq_uninstall(struct drm_device *dev)
-{
- DBG("dev=%p", dev);
- // TODO prolly need to call drm_irq_uninstall() somewhere too
-}
-
-/*
- * We need a special version, instead of just using drm_irq_install(),
- * because we need to register the irq via omapdss. Once omapdss and
- * omapdrm are merged together we can assign the dispc hwmod data to
- * ourselves and drop these and just use drm_irq_{install,uninstall}()
- */
-
-int omap_drm_irq_install(struct drm_device *dev)
-{
- int ret;
-
- mutex_lock(&dev->struct_mutex);
-
- if (dev->irq_enabled) {
- mutex_unlock(&dev->struct_mutex);
- return -EBUSY;
- }
- dev->irq_enabled = true;
- mutex_unlock(&dev->struct_mutex);
-
- /* Before installing handler */
- if (dev->driver->irq_preinstall)
- dev->driver->irq_preinstall(dev);
-
- ret = dispc_request_irq(dev->driver->irq_handler, dev);
-
- if (ret < 0) {
- mutex_lock(&dev->struct_mutex);
- dev->irq_enabled = false;
- mutex_unlock(&dev->struct_mutex);
- return ret;
- }
-
- /* After installing handler */
- if (dev->driver->irq_postinstall)
- ret = dev->driver->irq_postinstall(dev);
-
- if (ret < 0) {
- mutex_lock(&dev->struct_mutex);
- dev->irq_enabled = false;
- mutex_unlock(&dev->struct_mutex);
- dispc_free_irq(dev);
- }
-
- return ret;
-}
-
-int omap_drm_irq_uninstall(struct drm_device *dev)
+void omap_drm_irq_uninstall(struct drm_device *dev)
{
unsigned long irqflags;
- bool irq_enabled;
int i;
- mutex_lock(&dev->struct_mutex);
- irq_enabled = dev->irq_enabled;
- dev->irq_enabled = false;
- mutex_unlock(&dev->struct_mutex);
+ if (!dev->irq_enabled)
+ return;
- /*
- * Wake up any waiters so they don't hang.
- */
+ dev->irq_enabled = false;
+
+ /* Wake up any waiters so they don't hang. */
if (dev->num_crtcs) {
spin_lock_irqsave(&dev->vbl_lock, irqflags);
for (i = 0; i < dev->num_crtcs; i++) {
@@ -330,13 +278,5 @@
spin_unlock_irqrestore(&dev->vbl_lock, irqflags);
}
- if (!irq_enabled)
- return -EINVAL;
-
- if (dev->driver->irq_uninstall)
- dev->driver->irq_uninstall(dev);
-
dispc_free_irq(dev);
-
- return 0;
}
diff --git a/drivers/gpu/drm/omapdrm/omap_plane.c b/drivers/gpu/drm/omapdrm/omap_plane.c
index 1c6b63f..cfa8276 100644
--- a/drivers/gpu/drm/omapdrm/omap_plane.c
+++ b/drivers/gpu/drm/omapdrm/omap_plane.c
@@ -17,10 +17,11 @@
* this program. If not, see <http://www.gnu.org/licenses/>.
*/
-#include "drm_flip_work.h"
+#include <drm/drm_atomic_helper.h>
+#include <drm/drm_plane_helper.h>
-#include "omap_drv.h"
#include "omap_dmm_tiler.h"
+#include "omap_drv.h"
/* some hackery because omapdss has an 'enum omap_plane' (which would be
* better named omap_plane_id).. and compiler seems unhappy about having
@@ -32,237 +33,158 @@
* plane funcs
*/
-struct callback {
- void (*fxn)(void *);
- void *arg;
-};
-
#define to_omap_plane(x) container_of(x, struct omap_plane, base)
struct omap_plane {
struct drm_plane base;
int id; /* TODO rename omap_plane -> omap_plane_id in omapdss so I can use the enum */
const char *name;
- struct omap_overlay_info info;
- struct omap_drm_apply apply;
-
- /* position/orientation of scanout within the fb: */
- struct omap_drm_window win;
- bool enabled;
-
- /* last fb that we pinned: */
- struct drm_framebuffer *pinned_fb;
uint32_t nformats;
uint32_t formats[32];
struct omap_drm_irq error_irq;
-
- /* for deferring bo unpin's until next post_apply(): */
- struct drm_flip_work unpin_work;
-
- // XXX maybe get rid of this and handle vblank in crtc too?
- struct callback apply_done_cb;
};
-static void omap_plane_unpin_worker(struct drm_flip_work *work, void *val)
-{
- struct omap_plane *omap_plane =
- container_of(work, struct omap_plane, unpin_work);
- struct drm_device *dev = omap_plane->base.dev;
+struct omap_plane_state {
+ struct drm_plane_state base;
- /*
- * omap_framebuffer_pin/unpin are always called from priv->wq,
- * so there's no need for locking here.
- */
- omap_framebuffer_unpin(val);
- mutex_lock(&dev->mode_config.mutex);
- drm_framebuffer_unreference(val);
- mutex_unlock(&dev->mode_config.mutex);
+ unsigned int zorder;
+};
+
+static inline struct omap_plane_state *
+to_omap_plane_state(struct drm_plane_state *state)
+{
+ return container_of(state, struct omap_plane_state, base);
}
-/* update which fb (if any) is pinned for scanout */
-static int omap_plane_update_pin(struct drm_plane *plane,
- struct drm_framebuffer *fb)
+static int omap_plane_prepare_fb(struct drm_plane *plane,
+ struct drm_framebuffer *fb,
+ const struct drm_plane_state *new_state)
+{
+ return omap_framebuffer_pin(fb);
+}
+
+static void omap_plane_cleanup_fb(struct drm_plane *plane,
+ struct drm_framebuffer *fb,
+ const struct drm_plane_state *old_state)
+{
+ omap_framebuffer_unpin(fb);
+}
+
+static void omap_plane_atomic_update(struct drm_plane *plane,
+ struct drm_plane_state *old_state)
{
struct omap_plane *omap_plane = to_omap_plane(plane);
- struct drm_framebuffer *pinned_fb = omap_plane->pinned_fb;
-
- if (pinned_fb != fb) {
- int ret = 0;
-
- DBG("%p -> %p", pinned_fb, fb);
-
- if (fb) {
- drm_framebuffer_reference(fb);
- ret = omap_framebuffer_pin(fb);
- }
-
- if (pinned_fb)
- drm_flip_work_queue(&omap_plane->unpin_work, pinned_fb);
-
- if (ret) {
- dev_err(plane->dev->dev, "could not swap %p -> %p\n",
- omap_plane->pinned_fb, fb);
- drm_framebuffer_unreference(fb);
- omap_plane->pinned_fb = NULL;
- return ret;
- }
-
- omap_plane->pinned_fb = fb;
- }
-
- return 0;
-}
-
-static void omap_plane_pre_apply(struct omap_drm_apply *apply)
-{
- struct omap_plane *omap_plane =
- container_of(apply, struct omap_plane, apply);
- struct omap_drm_window *win = &omap_plane->win;
- struct drm_plane *plane = &omap_plane->base;
- struct drm_device *dev = plane->dev;
- struct omap_overlay_info *info = &omap_plane->info;
- struct drm_crtc *crtc = plane->crtc;
- enum omap_channel channel;
- bool enabled = omap_plane->enabled && crtc;
+ struct drm_plane_state *state = plane->state;
+ struct omap_plane_state *omap_state = to_omap_plane_state(state);
+ struct omap_overlay_info info;
+ struct omap_drm_window win;
int ret;
- DBG("%s, enabled=%d", omap_plane->name, enabled);
+ DBG("%s, crtc=%p fb=%p", omap_plane->name, state->crtc, state->fb);
- /* if fb has changed, pin new fb: */
- omap_plane_update_pin(plane, enabled ? plane->fb : NULL);
+ memset(&info, 0, sizeof(info));
+ info.rotation_type = OMAP_DSS_ROT_DMA;
+ info.rotation = OMAP_DSS_ROT_0;
+ info.global_alpha = 0xff;
+ info.mirror = 0;
+ info.zorder = omap_state->zorder;
- if (!enabled) {
- dispc_ovl_enable(omap_plane->id, false);
- return;
+ memset(&win, 0, sizeof(win));
+ win.rotation = state->rotation;
+ win.crtc_x = state->crtc_x;
+ win.crtc_y = state->crtc_y;
+ win.crtc_w = state->crtc_w;
+ win.crtc_h = state->crtc_h;
+
+ /*
+ * src values are in Q16 fixed point, convert to integer.
+ * omap_framebuffer_update_scanout() takes adjusted src.
+ */
+ win.src_x = state->src_x >> 16;
+ win.src_y = state->src_y >> 16;
+
+ switch (state->rotation & 0xf) {
+ case BIT(DRM_ROTATE_90):
+ case BIT(DRM_ROTATE_270):
+ win.src_w = state->src_h >> 16;
+ win.src_h = state->src_w >> 16;
+ break;
+ default:
+ win.src_w = state->src_w >> 16;
+ win.src_h = state->src_h >> 16;
+ break;
}
- channel = omap_crtc_channel(crtc);
-
/* update scanout: */
- omap_framebuffer_update_scanout(plane->fb, win, info);
+ omap_framebuffer_update_scanout(state->fb, &win, &info);
- DBG("%dx%d -> %dx%d (%d)", info->width, info->height,
- info->out_width, info->out_height,
- info->screen_width);
- DBG("%d,%d %pad %pad", info->pos_x, info->pos_y,
- &info->paddr, &info->p_uv_addr);
+ DBG("%dx%d -> %dx%d (%d)", info.width, info.height,
+ info.out_width, info.out_height,
+ info.screen_width);
+ DBG("%d,%d %pad %pad", info.pos_x, info.pos_y,
+ &info.paddr, &info.p_uv_addr);
- dispc_ovl_set_channel_out(omap_plane->id, channel);
+ dispc_ovl_set_channel_out(omap_plane->id,
+ omap_crtc_channel(state->crtc));
/* and finally, update omapdss: */
- ret = dispc_ovl_setup(omap_plane->id, info, false,
- omap_crtc_timings(crtc), false);
- if (ret) {
- dev_err(dev->dev, "dispc_ovl_setup failed: %d\n", ret);
+ ret = dispc_ovl_setup(omap_plane->id, &info, false,
+ omap_crtc_timings(state->crtc), false);
+ if (WARN_ON(ret)) {
+ dispc_ovl_enable(omap_plane->id, false);
return;
}
dispc_ovl_enable(omap_plane->id, true);
}
-static void omap_plane_post_apply(struct omap_drm_apply *apply)
+static void omap_plane_atomic_disable(struct drm_plane *plane,
+ struct drm_plane_state *old_state)
{
- struct omap_plane *omap_plane =
- container_of(apply, struct omap_plane, apply);
- struct drm_plane *plane = &omap_plane->base;
- struct omap_drm_private *priv = plane->dev->dev_private;
- struct callback cb;
+ struct omap_plane_state *omap_state = to_omap_plane_state(plane->state);
+ struct omap_plane *omap_plane = to_omap_plane(plane);
- cb = omap_plane->apply_done_cb;
- omap_plane->apply_done_cb.fxn = NULL;
+ plane->state->rotation = BIT(DRM_ROTATE_0);
+ omap_state->zorder = plane->type == DRM_PLANE_TYPE_PRIMARY
+ ? 0 : omap_plane->id;
- drm_flip_work_commit(&omap_plane->unpin_work, priv->wq);
-
- if (cb.fxn)
- cb.fxn(cb.arg);
+ dispc_ovl_enable(omap_plane->id, false);
}
-static int omap_plane_apply(struct drm_plane *plane)
-{
- if (plane->crtc) {
- struct omap_plane *omap_plane = to_omap_plane(plane);
- return omap_crtc_apply(plane->crtc, &omap_plane->apply);
- }
- return 0;
-}
+static const struct drm_plane_helper_funcs omap_plane_helper_funcs = {
+ .prepare_fb = omap_plane_prepare_fb,
+ .cleanup_fb = omap_plane_cleanup_fb,
+ .atomic_update = omap_plane_atomic_update,
+ .atomic_disable = omap_plane_atomic_disable,
+};
-int omap_plane_mode_set(struct drm_plane *plane,
- struct drm_crtc *crtc, struct drm_framebuffer *fb,
- int crtc_x, int crtc_y,
- unsigned int crtc_w, unsigned int crtc_h,
- unsigned int src_x, unsigned int src_y,
- unsigned int src_w, unsigned int src_h,
- void (*fxn)(void *), void *arg)
+static void omap_plane_reset(struct drm_plane *plane)
{
struct omap_plane *omap_plane = to_omap_plane(plane);
- struct omap_drm_window *win = &omap_plane->win;
+ struct omap_plane_state *omap_state;
- win->crtc_x = crtc_x;
- win->crtc_y = crtc_y;
- win->crtc_w = crtc_w;
- win->crtc_h = crtc_h;
+ if (plane->state && plane->state->fb)
+ drm_framebuffer_unreference(plane->state->fb);
- win->src_x = src_x;
- win->src_y = src_y;
- win->src_w = src_w;
- win->src_h = src_h;
+ kfree(plane->state);
+ plane->state = NULL;
- if (fxn) {
- /* omap_crtc should ensure that a new page flip
- * isn't permitted while there is one pending:
- */
- BUG_ON(omap_plane->apply_done_cb.fxn);
-
- omap_plane->apply_done_cb.fxn = fxn;
- omap_plane->apply_done_cb.arg = arg;
- }
-
- return omap_plane_apply(plane);
-}
-
-static int omap_plane_update(struct drm_plane *plane,
- struct drm_crtc *crtc, struct drm_framebuffer *fb,
- int crtc_x, int crtc_y,
- unsigned int crtc_w, unsigned int crtc_h,
- uint32_t src_x, uint32_t src_y,
- uint32_t src_w, uint32_t src_h)
-{
- struct omap_plane *omap_plane = to_omap_plane(plane);
- omap_plane->enabled = true;
-
- /* omap_plane_mode_set() takes adjusted src */
- switch (omap_plane->win.rotation & 0xf) {
- case BIT(DRM_ROTATE_90):
- case BIT(DRM_ROTATE_270):
- swap(src_w, src_h);
- break;
- }
+ omap_state = kzalloc(sizeof(*omap_state), GFP_KERNEL);
+ if (omap_state == NULL)
+ return;
/*
- * We don't need to take a reference to the framebuffer as the DRM core
- * has already done so for the purpose of setting plane->fb.
+ * Set defaults depending on whether we are a primary or overlay
+ * plane.
*/
- plane->fb = fb;
- plane->crtc = crtc;
+ omap_state->zorder = plane->type == DRM_PLANE_TYPE_PRIMARY
+ ? 0 : omap_plane->id;
+ omap_state->base.rotation = BIT(DRM_ROTATE_0);
- /* src values are in Q16 fixed point, convert to integer: */
- return omap_plane_mode_set(plane, crtc, fb,
- crtc_x, crtc_y, crtc_w, crtc_h,
- src_x >> 16, src_y >> 16, src_w >> 16, src_h >> 16,
- NULL, NULL);
-}
-
-static int omap_plane_disable(struct drm_plane *plane)
-{
- struct omap_plane *omap_plane = to_omap_plane(plane);
-
- omap_plane->win.rotation = BIT(DRM_ROTATE_0);
- omap_plane->info.zorder = plane->type == DRM_PLANE_TYPE_PRIMARY
- ? 0 : omap_plane->id;
-
- return omap_plane_set_enable(plane, false);
+ plane->state = &omap_state->base;
+ plane->state->plane = plane;
}
static void omap_plane_destroy(struct drm_plane *plane)
@@ -275,82 +197,94 @@
drm_plane_cleanup(plane);
- drm_flip_work_cleanup(&omap_plane->unpin_work);
-
kfree(omap_plane);
}
-int omap_plane_set_enable(struct drm_plane *plane, bool enable)
-{
- struct omap_plane *omap_plane = to_omap_plane(plane);
-
- if (enable == omap_plane->enabled)
- return 0;
-
- omap_plane->enabled = enable;
- return omap_plane_apply(plane);
-}
-
/* helper to install properties which are common to planes and crtcs */
void omap_plane_install_properties(struct drm_plane *plane,
struct drm_mode_object *obj)
{
struct drm_device *dev = plane->dev;
struct omap_drm_private *priv = dev->dev_private;
- struct drm_property *prop;
if (priv->has_dmm) {
- prop = priv->rotation_prop;
- if (!prop) {
- prop = drm_mode_create_rotation_property(dev,
- BIT(DRM_ROTATE_0) |
- BIT(DRM_ROTATE_90) |
- BIT(DRM_ROTATE_180) |
- BIT(DRM_ROTATE_270) |
- BIT(DRM_REFLECT_X) |
- BIT(DRM_REFLECT_Y));
- if (prop == NULL)
- return;
- priv->rotation_prop = prop;
- }
+ struct drm_property *prop = dev->mode_config.rotation_property;
+
drm_object_attach_property(obj, prop, 0);
}
- prop = priv->zorder_prop;
- if (!prop) {
- prop = drm_property_create_range(dev, 0, "zorder", 0, 3);
- if (prop == NULL)
- return;
- priv->zorder_prop = prop;
- }
- drm_object_attach_property(obj, prop, 0);
+ drm_object_attach_property(obj, priv->zorder_prop, 0);
}
-int omap_plane_set_property(struct drm_plane *plane,
- struct drm_property *property, uint64_t val)
+static struct drm_plane_state *
+omap_plane_atomic_duplicate_state(struct drm_plane *plane)
{
- struct omap_plane *omap_plane = to_omap_plane(plane);
+ struct omap_plane_state *state;
+ struct omap_plane_state *copy;
+
+ if (WARN_ON(!plane->state))
+ return NULL;
+
+ state = to_omap_plane_state(plane->state);
+ copy = kmemdup(state, sizeof(*state), GFP_KERNEL);
+ if (copy == NULL)
+ return NULL;
+
+ __drm_atomic_helper_plane_duplicate_state(plane, ©->base);
+
+ return ©->base;
+}
+
+static void omap_plane_atomic_destroy_state(struct drm_plane *plane,
+ struct drm_plane_state *state)
+{
+ __drm_atomic_helper_plane_destroy_state(plane, state);
+ kfree(to_omap_plane_state(state));
+}
+
+static int omap_plane_atomic_set_property(struct drm_plane *plane,
+ struct drm_plane_state *state,
+ struct drm_property *property,
+ uint64_t val)
+{
struct omap_drm_private *priv = plane->dev->dev_private;
- int ret = -EINVAL;
+ struct omap_plane_state *omap_state = to_omap_plane_state(state);
- if (property == priv->rotation_prop) {
- DBG("%s: rotation: %02x", omap_plane->name, (uint32_t)val);
- omap_plane->win.rotation = val;
- ret = omap_plane_apply(plane);
- } else if (property == priv->zorder_prop) {
- DBG("%s: zorder: %02x", omap_plane->name, (uint32_t)val);
- omap_plane->info.zorder = val;
- ret = omap_plane_apply(plane);
- }
+ if (property == priv->zorder_prop)
+ omap_state->zorder = val;
+ else
+ return -EINVAL;
- return ret;
+ return 0;
+}
+
+static int omap_plane_atomic_get_property(struct drm_plane *plane,
+ const struct drm_plane_state *state,
+ struct drm_property *property,
+ uint64_t *val)
+{
+ struct omap_drm_private *priv = plane->dev->dev_private;
+ const struct omap_plane_state *omap_state =
+ container_of(state, const struct omap_plane_state, base);
+
+ if (property == priv->zorder_prop)
+ *val = omap_state->zorder;
+ else
+ return -EINVAL;
+
+ return 0;
}
static const struct drm_plane_funcs omap_plane_funcs = {
- .update_plane = omap_plane_update,
- .disable_plane = omap_plane_disable,
+ .update_plane = drm_atomic_helper_update_plane,
+ .disable_plane = drm_atomic_helper_disable_plane,
+ .reset = omap_plane_reset,
.destroy = omap_plane_destroy,
- .set_property = omap_plane_set_property,
+ .set_property = drm_atomic_helper_plane_set_property,
+ .atomic_duplicate_state = omap_plane_atomic_duplicate_state,
+ .atomic_destroy_state = omap_plane_atomic_destroy_state,
+ .atomic_set_property = omap_plane_atomic_set_property,
+ .atomic_get_property = omap_plane_atomic_get_property,
};
static void omap_plane_error_irq(struct omap_drm_irq *irq, uint32_t irqstatus)
@@ -382,7 +316,6 @@
struct omap_drm_private *priv = dev->dev_private;
struct drm_plane *plane;
struct omap_plane *omap_plane;
- struct omap_overlay_info *info;
int ret;
DBG("%s: type=%d", plane_names[id], type);
@@ -391,9 +324,6 @@
if (!omap_plane)
return ERR_PTR(-ENOMEM);
- drm_flip_work_init(&omap_plane->unpin_work,
- "unpin", omap_plane_unpin_worker);
-
omap_plane->nformats = omap_framebuffer_get_formats(
omap_plane->formats, ARRAY_SIZE(omap_plane->formats),
dss_feat_get_supported_color_modes(id));
@@ -402,9 +332,6 @@
plane = &omap_plane->base;
- omap_plane->apply.pre_apply = omap_plane_pre_apply;
- omap_plane->apply.post_apply = omap_plane_post_apply;
-
omap_plane->error_irq.irqmask = error_irqs[id];
omap_plane->error_irq.irq = omap_plane_error_irq;
omap_irq_register(dev, &omap_plane->error_irq);
@@ -415,27 +342,10 @@
if (ret < 0)
goto error;
+ drm_plane_helper_add(plane, &omap_plane_helper_funcs);
+
omap_plane_install_properties(plane, &plane->base);
- /* get our starting configuration, set defaults for parameters
- * we don't currently use, etc:
- */
- info = &omap_plane->info;
- info->rotation_type = OMAP_DSS_ROT_DMA;
- info->rotation = OMAP_DSS_ROT_0;
- info->global_alpha = 0xff;
- info->mirror = 0;
-
- /* Set defaults depending on whether we are a CRTC or overlay
- * layer.
- * TODO add ioctl to give userspace an API to change this.. this
- * will come in a subsequent patch.
- */
- if (type == DRM_PLANE_TYPE_PRIMARY)
- omap_plane->info.zorder = 0;
- else
- omap_plane->info.zorder = id;
-
return plane;
error:
diff --git a/drivers/gpu/drm/panel/panel-ld9040.c b/drivers/gpu/drm/panel/panel-ld9040.c
index 08cf2c5..9c27bde 100644
--- a/drivers/gpu/drm/panel/panel-ld9040.c
+++ b/drivers/gpu/drm/panel/panel-ld9040.c
@@ -367,18 +367,18 @@
return 0;
}
-static struct of_device_id ld9040_of_match[] = {
+static const struct of_device_id ld9040_of_match[] = {
{ .compatible = "samsung,ld9040" },
{ }
};
MODULE_DEVICE_TABLE(of, ld9040_of_match);
static struct spi_driver ld9040_driver = {
- .probe = ld9040_probe,
- .remove = ld9040_remove,
+ .probe = ld9040_probe,
+ .remove = ld9040_remove,
.driver = {
- .name = "ld9040",
- .owner = THIS_MODULE,
+ .name = "ld9040",
+ .owner = THIS_MODULE,
.of_match_table = ld9040_of_match,
},
};
diff --git a/drivers/gpu/drm/panel/panel-s6e8aa0.c b/drivers/gpu/drm/panel/panel-s6e8aa0.c
index 144b273..3005110 100644
--- a/drivers/gpu/drm/panel/panel-s6e8aa0.c
+++ b/drivers/gpu/drm/panel/panel-s6e8aa0.c
@@ -1041,7 +1041,7 @@
return 0;
}
-static struct of_device_id s6e8aa0_of_match[] = {
+static const struct of_device_id s6e8aa0_of_match[] = {
{ .compatible = "samsung,s6e8aa0" },
{ }
};
diff --git a/drivers/gpu/drm/panel/panel-simple.c b/drivers/gpu/drm/panel/panel-simple.c
index 30904a9..f94201b 100644
--- a/drivers/gpu/drm/panel/panel-simple.c
+++ b/drivers/gpu/drm/panel/panel-simple.c
@@ -731,6 +731,30 @@
},
};
+static const struct display_timing hannstar_hsd100pxn1_timing = {
+ .pixelclock = { 55000000, 65000000, 75000000 },
+ .hactive = { 1024, 1024, 1024 },
+ .hfront_porch = { 40, 40, 40 },
+ .hback_porch = { 220, 220, 220 },
+ .hsync_len = { 20, 60, 100 },
+ .vactive = { 768, 768, 768 },
+ .vfront_porch = { 7, 7, 7 },
+ .vback_porch = { 21, 21, 21 },
+ .vsync_len = { 10, 10, 10 },
+ .flags = DISPLAY_FLAGS_DE_HIGH,
+};
+
+static const struct panel_desc hannstar_hsd100pxn1 = {
+ .timings = &hannstar_hsd100pxn1_timing,
+ .num_timings = 1,
+ .bpc = 6,
+ .size = {
+ .width = 203,
+ .height = 152,
+ },
+ .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG,
+};
+
static const struct drm_display_mode hitachi_tx23d38vm0caa_mode = {
.clock = 33333,
.hdisplay = 800,
@@ -872,6 +896,30 @@
},
};
+static const struct drm_display_mode lg_lb070wv8_mode = {
+ .clock = 33246,
+ .hdisplay = 800,
+ .hsync_start = 800 + 88,
+ .hsync_end = 800 + 88 + 80,
+ .htotal = 800 + 88 + 80 + 88,
+ .vdisplay = 480,
+ .vsync_start = 480 + 10,
+ .vsync_end = 480 + 10 + 25,
+ .vtotal = 480 + 10 + 25 + 10,
+ .vrefresh = 60,
+};
+
+static const struct panel_desc lg_lb070wv8 = {
+ .modes = &lg_lb070wv8_mode,
+ .num_modes = 1,
+ .bpc = 16,
+ .size = {
+ .width = 151,
+ .height = 91,
+ },
+ .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
+};
+
static const struct drm_display_mode lg_lp129qe_mode = {
.clock = 285250,
.hdisplay = 2560,
@@ -1038,6 +1086,9 @@
.compatible = "hannstar,hsd070pww1",
.data = &hannstar_hsd070pww1,
}, {
+ .compatible = "hannstar,hsd100pxn1",
+ .data = &hannstar_hsd100pxn1,
+ }, {
.compatible = "hit,tx23d38vm0caa",
.data = &hitachi_tx23d38vm0caa
}, {
@@ -1056,6 +1107,9 @@
.compatible = "innolux,zj070na-01p",
.data = &innolux_zj070na_01p,
}, {
+ .compatible = "lg,lb070wv8",
+ .data = &lg_lb070wv8,
+ }, {
.compatible = "lg,lp129qe",
.data = &lg_lp129qe,
}, {
diff --git a/drivers/gpu/drm/radeon/radeon.h b/drivers/gpu/drm/radeon/radeon.h
index 4d2d057..f03b7eb 100644
--- a/drivers/gpu/drm/radeon/radeon.h
+++ b/drivers/gpu/drm/radeon/radeon.h
@@ -2458,7 +2458,6 @@
/* amdkfd interface */
struct kfd_dev *kfd;
- struct radeon_sa_manager kfd_bo;
struct mutex mn_lock;
DECLARE_HASHTABLE(mn_hash, 7);
diff --git a/drivers/gpu/drm/rcar-du/rcar_du_crtc.c b/drivers/gpu/drm/rcar-du/rcar_du_crtc.c
index e6a32c4..65d6ba6 100644
--- a/drivers/gpu/drm/rcar-du/rcar_du_crtc.c
+++ b/drivers/gpu/drm/rcar-du/rcar_du_crtc.c
@@ -214,7 +214,7 @@
unsigned int i;
u32 dspr = 0;
- for (i = 0; i < ARRAY_SIZE(rcrtc->group->planes); ++i) {
+ for (i = 0; i < rcrtc->group->num_planes; ++i) {
struct rcar_du_plane *plane = &rcrtc->group->planes[i];
unsigned int j;
@@ -398,6 +398,19 @@
if (!rcrtc->started)
return;
+ /* Disable all planes and wait for the change to take effect. This is
+ * required as the DSnPR registers are updated on vblank, and no vblank
+ * will occur once the CRTC is stopped. Disabling planes when starting
+ * the CRTC thus wouldn't be enough as it would start scanning out
+ * immediately from old frame buffers until the next vblank.
+ *
+ * This increases the CRTC stop delay, especially when multiple CRTCs
+ * are stopped in one operation as we now wait for one vblank per CRTC.
+ * Whether this can be improved needs to be researched.
+ */
+ rcar_du_group_write(rcrtc->group, rcrtc->index % 2 ? DS2PR : DS1PR, 0);
+ drm_crtc_wait_one_vblank(crtc);
+
/* Disable vertical blanking interrupt reporting. We first need to wait
* for page flip completion before stopping the CRTC as userspace
* expects page flips to eventually complete.
@@ -432,7 +445,7 @@
rcar_du_crtc_start(rcrtc);
/* Commit the planes state. */
- for (i = 0; i < ARRAY_SIZE(rcrtc->group->planes); ++i) {
+ for (i = 0; i < rcrtc->group->num_planes; ++i) {
struct rcar_du_plane *plane = &rcrtc->group->planes[i];
if (plane->plane.state->crtc != &rcrtc->crtc)
diff --git a/drivers/gpu/drm/rcar-du/rcar_du_drv.c b/drivers/gpu/drm/rcar-du/rcar_du_drv.c
index da1216a..780ca11 100644
--- a/drivers/gpu/drm/rcar-du/rcar_du_drv.c
+++ b/drivers/gpu/drm/rcar-du/rcar_du_drv.c
@@ -190,7 +190,7 @@
/* DRM/KMS objects */
ret = rcar_du_modeset_init(rcdu);
if (ret < 0) {
- dev_err(&pdev->dev, "failed to initialize DRM/KMS\n");
+ dev_err(&pdev->dev, "failed to initialize DRM/KMS (%d)\n", ret);
goto done;
}
diff --git a/drivers/gpu/drm/rcar-du/rcar_du_group.h b/drivers/gpu/drm/rcar-du/rcar_du_group.h
index 7b414b3..d7318e1 100644
--- a/drivers/gpu/drm/rcar-du/rcar_du_group.h
+++ b/drivers/gpu/drm/rcar-du/rcar_du_group.h
@@ -30,6 +30,7 @@
* @used_crtcs: number of CRTCs currently in use
* @lock: protects the dptsr_planes field and the DPTSR register
* @dptsr_planes: bitmask of planes driven by dot-clock and timing generator 1
+ * @num_planes: number of planes in the group
* @planes: planes handled by the group
*/
struct rcar_du_group {
@@ -44,6 +45,7 @@
struct mutex lock;
unsigned int dptsr_planes;
+ unsigned int num_planes;
struct rcar_du_plane planes[RCAR_DU_NUM_KMS_PLANES];
};
diff --git a/drivers/gpu/drm/rcar-du/rcar_du_kms.c b/drivers/gpu/drm/rcar-du/rcar_du_kms.c
index 20859aa..56518eb 100644
--- a/drivers/gpu/drm/rcar-du/rcar_du_kms.c
+++ b/drivers/gpu/drm/rcar-du/rcar_du_kms.c
@@ -336,7 +336,7 @@
dev_dbg(rcdu->dev, "%s: finding free planes for group %u\n",
__func__, index);
- for (i = 0; i < RCAR_DU_NUM_KMS_PLANES; ++i) {
+ for (i = 0; i < group->num_planes; ++i) {
struct rcar_du_plane *plane = &group->planes[i];
struct rcar_du_plane_state *plane_state;
struct drm_plane_state *s;
@@ -495,8 +495,10 @@
/* Allocate the commit object. */
commit = kzalloc(sizeof(*commit), GFP_KERNEL);
- if (commit == NULL)
- return -ENOMEM;
+ if (commit == NULL) {
+ ret = -ENOMEM;
+ goto error;
+ }
INIT_WORK(&commit->work, rcar_du_atomic_work);
commit->dev = dev;
@@ -519,7 +521,7 @@
if (ret) {
kfree(commit);
- return ret;
+ goto error;
}
/* Swap the state, this is the point of no return. */
@@ -531,6 +533,10 @@
rcar_du_atomic_complete(commit);
return 0;
+
+error:
+ drm_atomic_helper_cleanup_planes(dev, state);
+ return ret;
}
/* -----------------------------------------------------------------------------
@@ -573,7 +579,7 @@
if (!entity) {
dev_dbg(rcdu->dev, "unconnected endpoint %s, skipping\n",
ep->local_node->full_name);
- return 0;
+ return -ENODEV;
}
entity_ep_node = of_parse_phandle(ep->local_node, "remote-endpoint", 0);
@@ -596,7 +602,7 @@
encoder->full_name);
of_node_put(entity_ep_node);
of_node_put(encoder);
- return 0;
+ return -ENODEV;
}
break;
@@ -625,7 +631,7 @@
encoder->full_name);
of_node_put(encoder);
of_node_put(connector);
- return 0;
+ return -EINVAL;
}
} else {
/*
@@ -639,7 +645,12 @@
of_node_put(encoder);
of_node_put(connector);
- return ret < 0 ? ret : 1;
+ if (ret && ret != -EPROBE_DEFER)
+ dev_warn(rcdu->dev,
+ "failed to initialize encoder %s (%d), skipping\n",
+ encoder->full_name, ret);
+
+ return ret;
}
static int rcar_du_encoders_init(struct rcar_du_device *rcdu)
@@ -688,12 +699,10 @@
return ret;
}
- dev_info(rcdu->dev,
- "encoder initialization failed, skipping\n");
continue;
}
- num_encoders += ret;
+ num_encoders++;
}
return num_encoders;
diff --git a/drivers/gpu/drm/rcar-du/rcar_du_plane.c b/drivers/gpu/drm/rcar-du/rcar_du_plane.c
index 3e30d84..c669864 100644
--- a/drivers/gpu/drm/rcar-du/rcar_du_plane.c
+++ b/drivers/gpu/drm/rcar-du/rcar_du_plane.c
@@ -302,13 +302,15 @@
struct rcar_du_plane_state *state;
struct rcar_du_plane_state *copy;
+ if (WARN_ON(!plane->state))
+ return NULL;
+
state = to_rcar_plane_state(plane->state);
copy = kmemdup(state, sizeof(*state), GFP_KERNEL);
if (copy == NULL)
return NULL;
- if (copy->state.fb)
- drm_framebuffer_reference(copy->state.fb);
+ __drm_atomic_helper_plane_duplicate_state(plane, ©->state);
return ©->state;
}
@@ -316,9 +318,7 @@
static void rcar_du_plane_atomic_destroy_state(struct drm_plane *plane,
struct drm_plane_state *state)
{
- if (state->fb)
- drm_framebuffer_unreference(state->fb);
-
+ __drm_atomic_helper_plane_destroy_state(plane, state);
kfree(to_rcar_plane_state(state));
}
@@ -390,7 +390,6 @@
int rcar_du_planes_init(struct rcar_du_group *rgrp)
{
struct rcar_du_device *rcdu = rgrp->dev;
- unsigned int num_planes;
unsigned int crtcs;
unsigned int i;
int ret;
@@ -398,11 +397,11 @@
/* Create one primary plane per CRTC in this group and seven overlay
* planes.
*/
- num_planes = rgrp->num_crtcs + 7;
+ rgrp->num_planes = rgrp->num_crtcs + 7;
crtcs = ((1 << rcdu->num_crtcs) - 1) & (3 << (2 * rgrp->index));
- for (i = 0; i < num_planes; ++i) {
+ for (i = 0; i < rgrp->num_planes; ++i) {
enum drm_plane_type type = i < rgrp->num_crtcs
? DRM_PLANE_TYPE_PRIMARY
: DRM_PLANE_TYPE_OVERLAY;
diff --git a/drivers/gpu/drm/tegra/dpaux.c b/drivers/gpu/drm/tegra/dpaux.c
index d6b55e3..07b2697 100644
--- a/drivers/gpu/drm/tegra/dpaux.c
+++ b/drivers/gpu/drm/tegra/dpaux.c
@@ -56,15 +56,14 @@
return container_of(work, struct tegra_dpaux, work);
}
-static inline unsigned long tegra_dpaux_readl(struct tegra_dpaux *dpaux,
- unsigned long offset)
+static inline u32 tegra_dpaux_readl(struct tegra_dpaux *dpaux,
+ unsigned long offset)
{
return readl(dpaux->regs + (offset << 2));
}
static inline void tegra_dpaux_writel(struct tegra_dpaux *dpaux,
- unsigned long value,
- unsigned long offset)
+ u32 value, unsigned long offset)
{
writel(value, dpaux->regs + (offset << 2));
}
@@ -72,34 +71,32 @@
static void tegra_dpaux_write_fifo(struct tegra_dpaux *dpaux, const u8 *buffer,
size_t size)
{
- unsigned long offset = DPAUX_DP_AUXDATA_WRITE(0);
size_t i, j;
- for (i = 0; i < size; i += 4) {
- size_t num = min_t(size_t, size - i, 4);
- unsigned long value = 0;
+ for (i = 0; i < DIV_ROUND_UP(size, 4); i++) {
+ size_t num = min_t(size_t, size - i * 4, 4);
+ u32 value = 0;
for (j = 0; j < num; j++)
- value |= buffer[i + j] << (j * 8);
+ value |= buffer[i * 4 + j] << (j * 8);
- tegra_dpaux_writel(dpaux, value, offset++);
+ tegra_dpaux_writel(dpaux, value, DPAUX_DP_AUXDATA_WRITE(i));
}
}
static void tegra_dpaux_read_fifo(struct tegra_dpaux *dpaux, u8 *buffer,
size_t size)
{
- unsigned long offset = DPAUX_DP_AUXDATA_READ(0);
size_t i, j;
- for (i = 0; i < size; i += 4) {
- size_t num = min_t(size_t, size - i, 4);
- unsigned long value;
+ for (i = 0; i < DIV_ROUND_UP(size, 4); i++) {
+ size_t num = min_t(size_t, size - i * 4, 4);
+ u32 value;
- value = tegra_dpaux_readl(dpaux, offset++);
+ value = tegra_dpaux_readl(dpaux, DPAUX_DP_AUXDATA_READ(i));
for (j = 0; j < num; j++)
- buffer[i + j] = value >> (j * 8);
+ buffer[i * 4 + j] = value >> (j * 8);
}
}
@@ -250,7 +247,7 @@
{
struct tegra_dpaux *dpaux = data;
irqreturn_t ret = IRQ_HANDLED;
- unsigned long value;
+ u32 value;
/* clear interrupts */
value = tegra_dpaux_readl(dpaux, DPAUX_INTR_AUX);
@@ -273,7 +270,7 @@
{
struct tegra_dpaux *dpaux;
struct resource *regs;
- unsigned long value;
+ u32 value;
int err;
dpaux = devm_kzalloc(&pdev->dev, sizeof(*dpaux), GFP_KERNEL);
@@ -465,7 +462,7 @@
enum drm_connector_status tegra_dpaux_detect(struct tegra_dpaux *dpaux)
{
- unsigned long value;
+ u32 value;
value = tegra_dpaux_readl(dpaux, DPAUX_DP_AUXSTAT);
@@ -477,7 +474,7 @@
int tegra_dpaux_enable(struct tegra_dpaux *dpaux)
{
- unsigned long value;
+ u32 value;
value = DPAUX_HYBRID_PADCTL_AUX_CMH(2) |
DPAUX_HYBRID_PADCTL_AUX_DRVZ(4) |
@@ -495,7 +492,7 @@
int tegra_dpaux_disable(struct tegra_dpaux *dpaux)
{
- unsigned long value;
+ u32 value;
value = tegra_dpaux_readl(dpaux, DPAUX_HYBRID_SPARE);
value |= DPAUX_HYBRID_SPARE_PAD_POWER_DOWN;
diff --git a/drivers/gpu/drm/tegra/drm.c b/drivers/gpu/drm/tegra/drm.c
index bfad15a..427f50c 100644
--- a/drivers/gpu/drm/tegra/drm.c
+++ b/drivers/gpu/drm/tegra/drm.c
@@ -124,14 +124,22 @@
return -ENOMEM;
if (iommu_present(&platform_bus_type)) {
+ struct iommu_domain_geometry *geometry;
+ u64 start, end;
+
tegra->domain = iommu_domain_alloc(&platform_bus_type);
if (!tegra->domain) {
err = -ENOMEM;
goto free;
}
- DRM_DEBUG("IOMMU context initialized\n");
- drm_mm_init(&tegra->mm, 0, SZ_2G);
+ geometry = &tegra->domain->geometry;
+ start = geometry->aperture_start;
+ end = geometry->aperture_end;
+
+ DRM_DEBUG("IOMMU context initialized (aperture: %#llx-%#llx)\n",
+ start, end);
+ drm_mm_init(&tegra->mm, start, end - start + 1);
}
mutex_init(&tegra->clients_lock);
diff --git a/drivers/gpu/drm/tegra/gem.c b/drivers/gpu/drm/tegra/gem.c
index 1217272..01e16e1 100644
--- a/drivers/gpu/drm/tegra/gem.c
+++ b/drivers/gpu/drm/tegra/gem.c
@@ -189,7 +189,6 @@
static int tegra_bo_get_pages(struct drm_device *drm, struct tegra_bo *bo)
{
struct scatterlist *s;
- struct sg_table *sgt;
unsigned int i;
bo->pages = drm_gem_get_pages(&bo->gem);
@@ -198,36 +197,28 @@
bo->num_pages = bo->gem.size >> PAGE_SHIFT;
- sgt = drm_prime_pages_to_sg(bo->pages, bo->num_pages);
- if (IS_ERR(sgt))
+ bo->sgt = drm_prime_pages_to_sg(bo->pages, bo->num_pages);
+ if (IS_ERR(bo->sgt))
goto put_pages;
/*
- * Fake up the SG table so that dma_map_sg() can be used to flush the
- * pages associated with it. Note that this relies on the fact that
- * the DMA API doesn't hook into IOMMU on Tegra, therefore mapping is
- * only cache maintenance.
+ * Fake up the SG table so that dma_sync_sg_for_device() can be used
+ * to flush the pages associated with it.
*
* TODO: Replace this by drm_clflash_sg() once it can be implemented
* without relying on symbols that are not exported.
*/
- for_each_sg(sgt->sgl, s, sgt->nents, i)
+ for_each_sg(bo->sgt->sgl, s, bo->sgt->nents, i)
sg_dma_address(s) = sg_phys(s);
- if (dma_map_sg(drm->dev, sgt->sgl, sgt->nents, DMA_TO_DEVICE) == 0)
- goto release_sgt;
-
- bo->sgt = sgt;
+ dma_sync_sg_for_device(drm->dev, bo->sgt->sgl, bo->sgt->nents,
+ DMA_TO_DEVICE);
return 0;
-release_sgt:
- sg_free_table(sgt);
- kfree(sgt);
- sgt = ERR_PTR(-ENOMEM);
put_pages:
drm_gem_put_pages(&bo->gem, bo->pages, false, false);
- return PTR_ERR(sgt);
+ return PTR_ERR(bo->sgt);
}
static int tegra_bo_alloc(struct drm_device *drm, struct tegra_bo *bo)
diff --git a/drivers/gpu/drm/virtio/virtgpu_drm_bus.c b/drivers/gpu/drm/virtio/virtgpu_drm_bus.c
index f4ec816..88a3916 100644
--- a/drivers/gpu/drm/virtio/virtgpu_drm_bus.c
+++ b/drivers/gpu/drm/virtio/virtgpu_drm_bus.c
@@ -37,6 +37,26 @@
return 0;
}
+static void virtio_pci_kick_out_firmware_fb(struct pci_dev *pci_dev)
+{
+ struct apertures_struct *ap;
+ bool primary;
+
+ ap = alloc_apertures(1);
+ if (!ap)
+ return;
+
+ ap->ranges[0].base = pci_resource_start(pci_dev, 0);
+ ap->ranges[0].size = pci_resource_len(pci_dev, 0);
+
+ primary = pci_dev->resource[PCI_ROM_RESOURCE].flags
+ & IORESOURCE_ROM_SHADOW;
+
+ remove_conflicting_framebuffers(ap, "virtiodrmfb", primary);
+
+ kfree(ap);
+}
+
int drm_virtio_init(struct drm_driver *driver, struct virtio_device *vdev)
{
struct drm_device *dev;
@@ -52,27 +72,11 @@
struct pci_dev *pdev = to_pci_dev(vdev->dev.parent);
bool vga = (pdev->class >> 8) == PCI_CLASS_DISPLAY_VGA;
- if (vga) {
- /*
- * Need to make sure we don't have two drivers
- * for the same hardware here. Some day we
- * will simply kick out the firmware
- * (vesa/efi) framebuffer.
- *
- * Virtual hardware specs for virtio-vga are
- * not finalized yet, therefore we can't add
- * code for that yet.
- *
- * So ignore the device for the time being,
- * and suggest to the user use the device
- * variant without vga compatibility mode.
- */
- DRM_ERROR("virtio-vga not (yet) supported\n");
- DRM_ERROR("please use virtio-gpu-pci instead\n");
- ret = -ENODEV;
- goto err_free;
- }
+ DRM_INFO("pci: %s detected\n",
+ vga ? "virtio-vga" : "virtio-gpu-pci");
dev->pdev = pdev;
+ if (vga)
+ virtio_pci_kick_out_firmware_fb(pdev);
}
ret = drm_dev_register(dev, 0);
diff --git a/drivers/gpu/drm/virtio/virtgpu_drv.h b/drivers/gpu/drm/virtio/virtgpu_drv.h
index e5a2c09..6d4db2d 100644
--- a/drivers/gpu/drm/virtio/virtgpu_drv.h
+++ b/drivers/gpu/drm/virtio/virtgpu_drv.h
@@ -162,6 +162,7 @@
struct virtio_gpu_queue ctrlq;
struct virtio_gpu_queue cursorq;
struct list_head free_vbufs;
+ spinlock_t free_vbufs_lock;
void *vbufs;
bool vqs_ready;
@@ -171,6 +172,7 @@
wait_queue_head_t resp_wq;
/* current display info */
spinlock_t display_info_lock;
+ bool display_info_pending;
struct virtio_gpu_fence_driver fence_drv;
diff --git a/drivers/gpu/drm/virtio/virtgpu_kms.c b/drivers/gpu/drm/virtio/virtgpu_kms.c
index 132405f..782766c 100644
--- a/drivers/gpu/drm/virtio/virtgpu_kms.c
+++ b/drivers/gpu/drm/virtio/virtgpu_kms.c
@@ -137,9 +137,11 @@
virtio_device_ready(vgdev->vdev);
vgdev->vqs_ready = true;
+ virtio_gpu_cmd_get_display_info(vgdev);
+ wait_event_timeout(vgdev->resp_wq, !vgdev->display_info_pending,
+ 5 * HZ);
if (virtio_gpu_fbdev)
virtio_gpu_fbdev_init(vgdev);
- virtio_gpu_cmd_get_display_info(vgdev);
return 0;
diff --git a/drivers/gpu/drm/virtio/virtgpu_vq.c b/drivers/gpu/drm/virtio/virtgpu_vq.c
index 8fa6513e..1698669f 100644
--- a/drivers/gpu/drm/virtio/virtgpu_vq.c
+++ b/drivers/gpu/drm/virtio/virtgpu_vq.c
@@ -79,6 +79,7 @@
void *ptr;
INIT_LIST_HEAD(&vgdev->free_vbufs);
+ spin_lock_init(&vgdev->free_vbufs_lock);
count += virtqueue_get_vring_size(vgdev->ctrlq.vq);
count += virtqueue_get_vring_size(vgdev->cursorq.vq);
size = count * VBUFFER_SIZE;
@@ -106,6 +107,7 @@
count += virtqueue_get_vring_size(vgdev->ctrlq.vq);
count += virtqueue_get_vring_size(vgdev->cursorq.vq);
+ spin_lock(&vgdev->free_vbufs_lock);
for (i = 0; i < count; i++) {
if (WARN_ON(list_empty(&vgdev->free_vbufs)))
return;
@@ -113,6 +115,7 @@
struct virtio_gpu_vbuffer, list);
list_del(&vbuf->list);
}
+ spin_unlock(&vgdev->free_vbufs_lock);
kfree(vgdev->vbufs);
}
@@ -123,10 +126,12 @@
{
struct virtio_gpu_vbuffer *vbuf;
+ spin_lock(&vgdev->free_vbufs_lock);
BUG_ON(list_empty(&vgdev->free_vbufs));
vbuf = list_first_entry(&vgdev->free_vbufs,
struct virtio_gpu_vbuffer, list);
list_del(&vbuf->list);
+ spin_unlock(&vgdev->free_vbufs_lock);
memset(vbuf, 0, VBUFFER_SIZE);
BUG_ON(size > MAX_INLINE_CMD_SIZE);
@@ -201,7 +206,9 @@
if (vbuf->resp_size > MAX_INLINE_RESP_SIZE)
kfree(vbuf->resp_buf);
kfree(vbuf->data_buf);
+ spin_lock(&vgdev->free_vbufs_lock);
list_add(&vbuf->list, &vgdev->free_vbufs);
+ spin_unlock(&vgdev->free_vbufs_lock);
}
static void reclaim_vbufs(struct virtqueue *vq, struct list_head *reclaim_list)
@@ -534,6 +541,7 @@
}
}
+ vgdev->display_info_pending = false;
spin_unlock(&vgdev->display_info_lock);
wake_up(&vgdev->resp_wq);
@@ -558,6 +566,7 @@
resp_buf);
memset(cmd_p, 0, sizeof(*cmd_p));
+ vgdev->display_info_pending = true;
cmd_p->type = cpu_to_le32(VIRTIO_GPU_CMD_GET_DISPLAY_INFO);
virtio_gpu_queue_ctrl_buffer(vgdev, vbuf);
return 0;
diff --git a/include/drm/bridge/ptn3460.h b/include/drm/bridge/ptn3460.h
deleted file mode 100644
index b11f8e1..0000000
--- a/include/drm/bridge/ptn3460.h
+++ /dev/null
@@ -1,45 +0,0 @@
-/*
- * Copyright (C) 2013 Google, Inc.
- *
- * This software is licensed under the terms of the GNU General Public
- * License version 2, as published by the Free Software Foundation, and
- * may be copied, distributed, and modified under those terms.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#ifndef _DRM_BRIDGE_PTN3460_H_
-#define _DRM_BRIDGE_PTN3460_H_
-
-struct drm_device;
-struct drm_bridge;
-struct drm_encoder;
-struct i2c_client;
-struct device_node;
-
-#if defined(CONFIG_DRM_PTN3460) || defined(CONFIG_DRM_PTN3460_MODULE)
-
-int ptn3460_init(struct drm_device *dev, struct drm_encoder *encoder,
- struct i2c_client *client, struct device_node *node);
-
-void ptn3460_destroy(struct drm_bridge *bridge);
-
-#else
-
-static inline int ptn3460_init(struct drm_device *dev,
- struct drm_encoder *encoder, struct i2c_client *client,
- struct device_node *node)
-{
- return 0;
-}
-
-static inline void ptn3460_destroy(struct drm_bridge *bridge)
-{
-}
-
-#endif
-
-#endif