tree dd5d12e53b34f610a6f668504fe8ffb9ca063d3f
parent e387088a03a07583f248a237cb00c5c955a394c9
parent e142a4e91443d0fc2185c821626e66729f323d1c
author Michael Turquette <mturquette@linaro.org> 1422404772 -0800
committer Michael Turquette <mturquette@linaro.org> 1422404772 -0800
mergetag object e142a4e91443d0fc2185c821626e66729f323d1c
 type commit
 tag v3.20-rockchip-clk1
 tagger Heiko Stuebner <heiko@sntech.de> 1421942172 +0100
 
 The two big changes are the additional of the watchdog clock, which
 we currently only "fake" as the clock gate control is living in a
 very strange place, but the watchdog driver needs to read the clock
 rate from it and the setting of rk3288 plls to slow mode upon suspend.
 
 Other than that some more exported clocks and a CLK_SET_RATE_PARENT
 flag for the uart clocks.
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Merge tag 'v3.20-rockchip-clk1' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip into clk-next

The two big changes are the additional of the watchdog clock, which
we currently only "fake" as the clock gate control is living in a
very strange place, but the watchdog driver needs to read the clock
rate from it and the setting of rk3288 plls to slow mode upon suspend.

Other than that some more exported clocks and a CLK_SET_RATE_PARENT
flag for the uart clocks.