tree 02939e404694eb0067b149d54c6191fea04de68f
parent ed1bbdefc39477a1301fb466139ffb0c00f0d006
author Wu Zhangjin <wuzhangjin@gmail.com> 1271135794 +0800
committer Ralf Baechle <ralf@linux-mips.org> 1274473874 +0100

MIPS: Loongson: update cpu-feature-overrides.h

Loongson doesn't support MIPSR2, therefore, MIPSR2 vectored interrupts
(cpu_has_vint) and MIPSR2 external interrupt controller mode
(cpu_has_veic) are 0.

Signed-off-by: Wu Zhangjin <wuzhangjin@gmail.com>
Cc: Linux-MIPS <linux-mips@linux-mips.org>
Patchwork: http://patchwork.linux-mips.org/patch/1112/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>