| commit | b89cd950cbcd6a6aca37e82ecf369ab9909fdf24 | [log] [tgz] |
|---|---|---|
| author | Dinh Nguyen <dinguyen@altera.com> | Wed Feb 19 15:11:11 2014 -0600 |
| committer | Mike Turquette <mturquette@linaro.org> | Wed Feb 26 12:23:40 2014 -0800 |
| tree | 711a1ada6d863af2fe3f8022d27820c7bd479a0e | |
| parent | 5585f7317573873f95c1bb7748322c62a6c3a919 [diff] |
clk: socfpga: Support multiple parents for the pll clocks The PLLs can be from 3 different sources: osc1, osc2, or the f2s_ref_clk. Update the clock driver to be able to get the correct parent. Signed-off-by: Dinh Nguyen <dinguyen@altera.com> Cc: Steffen Trumtrar <s.trumtrar@pengutronix.de> Signed-off-by: Mike Turquette <mturquette@linaro.org>