| commit | b8f3ebe630a4f1b4ff9340103d3b565ad5d78d43 | [log] [tgz] |
|---|---|---|
| author | Minghuan Lian <Minghuan.Lian@nxp.com> | Wed Mar 23 19:08:20 2016 +0800 |
| committer | Marc Zyngier <marc.zyngier@arm.com> | Wed May 04 09:58:04 2016 +0100 |
| tree | 9072b01dd90206a5908274e8d91337c1ca41badf | |
| parent | 5e79cb29ddbd1d354398308309337ba013245469 [diff] |
irqchip: Add Layerscape SCFG MSI controller support Some kind of Freescale Layerscape SoC provides a MSI implementation which uses two SCFG registers MSIIR and MSIR to support 32 MSI interrupts for each PCIe controller. The patch is to support it. Signed-off-by: Minghuan Lian <Minghuan.Lian@nxp.com> Tested-by: Alexander Stein <alexander.stein@systec-electronic.com> Acked-by: Marc Zyngier <marc.zyngier@arm.com> Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>