| commit | b8f9a02924bbeb0c46ca4c19561cbe765b80e264 | [log] [tgz] |
|---|---|---|
| author | Florian Fainelli <f.fainelli@gmail.com> | Fri Aug 22 18:55:45 2014 -0700 |
| committer | David S. Miller <davem@davemloft.net> | Sat Aug 23 11:39:09 2014 -0700 |
| tree | 6990b37910085fec8a0b832f807d9e2c22ff73de | |
| parent | a9f6309585cbefa4a7f08c9017ca482c3222323a [diff] |
net: phy: bcm7xxx: enable EEE at the PHY level The 28nm Gigabit PHY on BCM7xxx chips comes out of reset with absolutely no EEE capabilities, such that we would actually return that we do not support EEE when accessing 3.20 (MDIO_PCS_EEE_ABLE) registers. Poke through the vendor-specific C45 register to enable EEE globally at the PHY level, and advertise supported EEE modes. Signed-off-by: Florian Fainelli <f.fainelli@gmail.com> Signed-off-by: David S. Miller <davem@davemloft.net>