tree 1a1db94b0ffb90cd25d65ae8e419acbd6673e8c7
parent e6f0bfc4fb963da9e945ebc6330db9a4d756ba78
author Paulo Zanoni <paulo.r.zanoni@intel.com> 1351024205 -0200
committer Daniel Vetter <daniel.vetter@ffwll.ch> 1351239890 +0200

drm/i915: set the correct eDP aux channel clock divider on DDI

The cdclk frequency is not always the same, so the value here should
be adjusted to match it.

Version 2: call intel_ddi_get_cdclk_freq instead of reading
CDCLK_FREQ, because the register is just for earlier HW steppings.

Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Reviewed-by: Rodrigo Vivi <rodrigo.vivi@gmail.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>