mmc: sdhci-msm: select pin drive type for each clock rate
SDHCI uses fixed two drive types, which are active and
sleep. This change adds supporting for choosing specific
drive type for each given clock rate. It is implemented
by selecting drive types, if given by device tree, after
clock rate is changed.
Change-Id: I45171f79f0b6a481ee51ef2673872eba756e5d0a
Signed-off-by: Can Guo <cang@codeaurora.org>
diff --git a/drivers/mmc/host/sdhci-msm.c b/drivers/mmc/host/sdhci-msm.c
index 6b018e1..32da1fd 100644
--- a/drivers/mmc/host/sdhci-msm.c
+++ b/drivers/mmc/host/sdhci-msm.c
@@ -1406,6 +1406,32 @@
return ret;
}
+static int sdhci_msm_config_pinctrl_drv_type(struct sdhci_msm_pltfm_data *pdata,
+ unsigned int clock)
+{
+ int ret = 0;
+
+ if (clock > 150000000) {
+ if (pdata->pctrl_data->pins_drv_type_200MHz)
+ ret = pinctrl_select_state(pdata->pctrl_data->pctrl,
+ pdata->pctrl_data->pins_drv_type_200MHz);
+ } else if (clock > 75000000) {
+ if (pdata->pctrl_data->pins_drv_type_100MHz)
+ ret = pinctrl_select_state(pdata->pctrl_data->pctrl,
+ pdata->pctrl_data->pins_drv_type_100MHz);
+ } else if (clock > 400000) {
+ if (pdata->pctrl_data->pins_drv_type_50MHz)
+ ret = pinctrl_select_state(pdata->pctrl_data->pctrl,
+ pdata->pctrl_data->pins_drv_type_50MHz);
+ } else {
+ if (pdata->pctrl_data->pins_drv_type_400KHz)
+ ret = pinctrl_select_state(pdata->pctrl_data->pctrl,
+ pdata->pctrl_data->pins_drv_type_400KHz);
+ }
+
+ return ret;
+}
+
static int sdhci_msm_setup_pinctrl(struct sdhci_msm_pltfm_data *pdata,
bool enable)
{
@@ -1586,6 +1612,27 @@
dev_err(dev, "Could not get sleep pinstates, err:%d\n", ret);
goto out;
}
+
+ pctrl_data->pins_drv_type_400KHz = pinctrl_lookup_state(
+ pctrl_data->pctrl, "ds_400KHz");
+ if (IS_ERR(pctrl_data->pins_drv_type_400KHz))
+ dev_dbg(dev, "Could not get 400K pinstates, err:%d\n", ret);
+
+ pctrl_data->pins_drv_type_50MHz = pinctrl_lookup_state(
+ pctrl_data->pctrl, "ds_50MHz");
+ if (IS_ERR(pctrl_data->pins_drv_type_50MHz))
+ dev_dbg(dev, "Could not get 50M pinstates, err:%d\n", ret);
+
+ pctrl_data->pins_drv_type_100MHz = pinctrl_lookup_state(
+ pctrl_data->pctrl, "ds_100MHz");
+ if (IS_ERR(pctrl_data->pins_drv_type_100MHz))
+ dev_dbg(dev, "Could not get 100M pinstates, err:%d\n", ret);
+
+ pctrl_data->pins_drv_type_200MHz = pinctrl_lookup_state(
+ pctrl_data->pctrl, "ds_200MHz");
+ if (IS_ERR(pctrl_data->pins_drv_type_200MHz))
+ dev_dbg(dev, "Could not get 200M pinstates, err:%d\n", ret);
+
pdata->pctrl_data = pctrl_data;
out:
return ret;
@@ -3349,6 +3396,16 @@
}
msm_host->clk_rate = sup_clock;
host->clock = clock;
+
+ /* Configure pinctrl drive type according to
+ * current clock rate
+ */
+ rc = sdhci_msm_config_pinctrl_drv_type(msm_host->pdata, clock);
+ if (rc)
+ pr_err("%s: %s: Failed to set pinctrl drive type for clock rate %u (%d)\n",
+ mmc_hostname(host->mmc), __func__,
+ clock, rc);
+
/*
* Update the bus vote in case of frequency change due to
* clock scaling.
diff --git a/drivers/mmc/host/sdhci-msm.h b/drivers/mmc/host/sdhci-msm.h
index 2c6c0d7..6e15a73 100644
--- a/drivers/mmc/host/sdhci-msm.h
+++ b/drivers/mmc/host/sdhci-msm.h
@@ -76,6 +76,10 @@
struct pinctrl *pctrl;
struct pinctrl_state *pins_active;
struct pinctrl_state *pins_sleep;
+ struct pinctrl_state *pins_drv_type_400KHz;
+ struct pinctrl_state *pins_drv_type_50MHz;
+ struct pinctrl_state *pins_drv_type_100MHz;
+ struct pinctrl_state *pins_drv_type_200MHz;
};
struct sdhci_msm_bus_voting_data {