| /* |
| * MPC8641 HPCN Device Tree Source |
| * |
| * Copyright 2006 Freescale Semiconductor Inc. |
| * |
| * This program is free software; you can redistribute it and/or modify it |
| * under the terms of the GNU General Public License as published by the |
| * Free Software Foundation; either version 2 of the License, or (at your |
| * option) any later version. |
| */ |
| |
| |
| / { |
| model = "MPC8641HPCN"; |
| compatible = "mpc86xx"; |
| #address-cells = <1>; |
| #size-cells = <1>; |
| |
| cpus { |
| #cpus = <2>; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| |
| PowerPC,8641@0 { |
| device_type = "cpu"; |
| reg = <0>; |
| d-cache-line-size = <20>; // 32 bytes |
| i-cache-line-size = <20>; // 32 bytes |
| d-cache-size = <8000>; // L1, 32K |
| i-cache-size = <8000>; // L1, 32K |
| timebase-frequency = <0>; // 33 MHz, from uboot |
| bus-frequency = <0>; // From uboot |
| clock-frequency = <0>; // From uboot |
| 32-bit; |
| }; |
| PowerPC,8641@1 { |
| device_type = "cpu"; |
| reg = <1>; |
| d-cache-line-size = <20>; // 32 bytes |
| i-cache-line-size = <20>; // 32 bytes |
| d-cache-size = <8000>; // L1, 32K |
| i-cache-size = <8000>; // L1, 32K |
| timebase-frequency = <0>; // 33 MHz, from uboot |
| bus-frequency = <0>; // From uboot |
| clock-frequency = <0>; // From uboot |
| 32-bit; |
| }; |
| }; |
| |
| memory { |
| device_type = "memory"; |
| reg = <00000000 40000000>; // 1G at 0x0 |
| }; |
| |
| soc8641@f8000000 { |
| #address-cells = <1>; |
| #size-cells = <1>; |
| #interrupt-cells = <2>; |
| device_type = "soc"; |
| ranges = <0 f8000000 00100000>; |
| reg = <f8000000 00100000>; // CCSRBAR 1M |
| bus-frequency = <0>; |
| |
| i2c@3000 { |
| device_type = "i2c"; |
| compatible = "fsl-i2c"; |
| reg = <3000 100>; |
| interrupts = <2b 2>; |
| interrupt-parent = <&mpic>; |
| dfsrr; |
| }; |
| |
| i2c@3100 { |
| device_type = "i2c"; |
| compatible = "fsl-i2c"; |
| reg = <3100 100>; |
| interrupts = <2b 2>; |
| interrupt-parent = <&mpic>; |
| dfsrr; |
| }; |
| |
| mdio@24520 { |
| #address-cells = <1>; |
| #size-cells = <0>; |
| device_type = "mdio"; |
| compatible = "gianfar"; |
| reg = <24520 20>; |
| phy0: ethernet-phy@0 { |
| interrupt-parent = <&mpic>; |
| interrupts = <4a 1>; |
| reg = <0>; |
| device_type = "ethernet-phy"; |
| }; |
| phy1: ethernet-phy@1 { |
| interrupt-parent = <&mpic>; |
| interrupts = <4a 1>; |
| reg = <1>; |
| device_type = "ethernet-phy"; |
| }; |
| phy2: ethernet-phy@2 { |
| interrupt-parent = <&mpic>; |
| interrupts = <4a 1>; |
| reg = <2>; |
| device_type = "ethernet-phy"; |
| }; |
| phy3: ethernet-phy@3 { |
| interrupt-parent = <&mpic>; |
| interrupts = <4a 1>; |
| reg = <3>; |
| device_type = "ethernet-phy"; |
| }; |
| }; |
| |
| ethernet@24000 { |
| #address-cells = <1>; |
| #size-cells = <0>; |
| device_type = "network"; |
| model = "TSEC"; |
| compatible = "gianfar"; |
| reg = <24000 1000>; |
| mac-address = [ 00 E0 0C 00 73 00 ]; |
| interrupts = <1d 2 1e 2 22 2>; |
| interrupt-parent = <&mpic>; |
| phy-handle = <&phy0>; |
| }; |
| |
| ethernet@25000 { |
| #address-cells = <1>; |
| #size-cells = <0>; |
| device_type = "network"; |
| model = "TSEC"; |
| compatible = "gianfar"; |
| reg = <25000 1000>; |
| mac-address = [ 00 E0 0C 00 73 01 ]; |
| interrupts = <23 2 24 2 28 2>; |
| interrupt-parent = <&mpic>; |
| phy-handle = <&phy1>; |
| }; |
| |
| ethernet@26000 { |
| #address-cells = <1>; |
| #size-cells = <0>; |
| device_type = "network"; |
| model = "TSEC"; |
| compatible = "gianfar"; |
| reg = <26000 1000>; |
| mac-address = [ 00 E0 0C 00 02 FD ]; |
| interrupts = <1F 2 20 2 21 2>; |
| interrupt-parent = <&mpic>; |
| phy-handle = <&phy2>; |
| }; |
| |
| ethernet@27000 { |
| #address-cells = <1>; |
| #size-cells = <0>; |
| device_type = "network"; |
| model = "TSEC"; |
| compatible = "gianfar"; |
| reg = <27000 1000>; |
| mac-address = [ 00 E0 0C 00 03 FD ]; |
| interrupts = <25 2 26 2 27 2>; |
| interrupt-parent = <&mpic>; |
| phy-handle = <&phy3>; |
| }; |
| serial@4500 { |
| device_type = "serial"; |
| compatible = "ns16550"; |
| reg = <4500 100>; |
| clock-frequency = <0>; |
| interrupts = <2a 2>; |
| interrupt-parent = <&mpic>; |
| }; |
| |
| serial@4600 { |
| device_type = "serial"; |
| compatible = "ns16550"; |
| reg = <4600 100>; |
| clock-frequency = <0>; |
| interrupts = <1c 2>; |
| interrupt-parent = <&mpic>; |
| }; |
| |
| pci@8000 { |
| compatible = "86xx"; |
| device_type = "pci"; |
| #interrupt-cells = <1>; |
| #size-cells = <2>; |
| #address-cells = <3>; |
| reg = <8000 1000>; |
| bus-range = <0 fe>; |
| ranges = <02000000 0 80000000 80000000 0 20000000 |
| 01000000 0 00000000 e2000000 0 00100000>; |
| clock-frequency = <1fca055>; |
| interrupt-parent = <&mpic>; |
| interrupts = <18 2>; |
| interrupt-map-mask = <f800 0 0 7>; |
| interrupt-map = < |
| /* IDSEL 0x11 */ |
| 8800 0 0 1 &i8259 3 2 |
| 8800 0 0 2 &i8259 4 2 |
| 8800 0 0 3 &i8259 5 2 |
| 8800 0 0 4 &i8259 6 2 |
| |
| /* IDSEL 0x12 */ |
| 9000 0 0 1 &i8259 4 2 |
| 9000 0 0 2 &i8259 5 2 |
| 9000 0 0 3 &i8259 6 2 |
| 9000 0 0 4 &i8259 3 2 |
| |
| /* IDSEL 0x13 */ |
| 9800 0 0 1 &i8259 0 0 |
| 9800 0 0 2 &i8259 0 0 |
| 9800 0 0 3 &i8259 0 0 |
| 9800 0 0 4 &i8259 0 0 |
| |
| /* IDSEL 0x14 */ |
| a000 0 0 1 &i8259 0 0 |
| a000 0 0 2 &i8259 0 0 |
| a000 0 0 3 &i8259 0 0 |
| a000 0 0 4 &i8259 0 0 |
| |
| /* IDSEL 0x15 */ |
| a800 0 0 1 &i8259 0 0 |
| a800 0 0 2 &i8259 0 0 |
| a800 0 0 3 &i8259 0 0 |
| a800 0 0 4 &i8259 0 0 |
| |
| /* IDSEL 0x16 */ |
| b000 0 0 1 &i8259 0 0 |
| b000 0 0 2 &i8259 0 0 |
| b000 0 0 3 &i8259 0 0 |
| b000 0 0 4 &i8259 0 0 |
| |
| /* IDSEL 0x17 */ |
| b800 0 0 1 &i8259 0 0 |
| b800 0 0 2 &i8259 0 0 |
| b800 0 0 3 &i8259 0 0 |
| b800 0 0 4 &i8259 0 0 |
| |
| /* IDSEL 0x18 */ |
| c000 0 0 1 &i8259 0 0 |
| c000 0 0 2 &i8259 0 0 |
| c000 0 0 3 &i8259 0 0 |
| c000 0 0 4 &i8259 0 0 |
| |
| /* IDSEL 0x19 */ |
| c800 0 0 1 &i8259 0 0 |
| c800 0 0 2 &i8259 0 0 |
| c800 0 0 3 &i8259 0 0 |
| c800 0 0 4 &i8259 0 0 |
| |
| /* IDSEL 0x1a */ |
| d000 0 0 1 &i8259 6 2 |
| d000 0 0 2 &i8259 3 2 |
| d000 0 0 3 &i8259 4 2 |
| d000 0 0 4 &i8259 5 2 |
| |
| |
| /* IDSEL 0x1b */ |
| d800 0 0 1 &i8259 5 2 |
| d800 0 0 2 &i8259 0 0 |
| d800 0 0 3 &i8259 0 0 |
| d800 0 0 4 &i8259 0 0 |
| |
| /* IDSEL 0x1c */ |
| e000 0 0 1 &i8259 9 2 |
| e000 0 0 2 &i8259 a 2 |
| e000 0 0 3 &i8259 c 2 |
| e000 0 0 4 &i8259 7 2 |
| |
| /* IDSEL 0x1d */ |
| e800 0 0 1 &i8259 9 2 |
| e800 0 0 2 &i8259 a 2 |
| e800 0 0 3 &i8259 b 2 |
| e800 0 0 4 &i8259 0 0 |
| |
| /* IDSEL 0x1e */ |
| f000 0 0 1 &i8259 c 2 |
| f000 0 0 2 &i8259 0 0 |
| f000 0 0 3 &i8259 0 0 |
| f000 0 0 4 &i8259 0 0 |
| |
| /* IDSEL 0x1f */ |
| f800 0 0 1 &i8259 6 2 |
| f800 0 0 2 &i8259 0 0 |
| f800 0 0 3 &i8259 0 0 |
| f800 0 0 4 &i8259 0 0 |
| >; |
| i8259: i8259@4d0 { |
| clock-frequency = <0>; |
| interrupt-controller; |
| device_type = "interrupt-controller"; |
| #address-cells = <0>; |
| #interrupt-cells = <2>; |
| built-in; |
| compatible = "chrp,iic"; |
| big-endian; |
| interrupts = <49 2>; |
| interrupt-parent = <&mpic>; |
| }; |
| |
| }; |
| mpic: pic@40000 { |
| clock-frequency = <0>; |
| interrupt-controller; |
| #address-cells = <0>; |
| #interrupt-cells = <2>; |
| reg = <40000 40000>; |
| built-in; |
| compatible = "chrp,open-pic"; |
| device_type = "open-pic"; |
| big-endian; |
| }; |
| }; |
| }; |