tree bab61165c96cd1b762250d7de593b88580fd43a4
parent 938cc3a14ca0d921165c741fb10d8defba203dde
author Santosh Shilimkar <santosh.shilimkar@ti.com> 1380158293 -0400
committer Mike Turquette <mturquette@linaro.org> 1381194981 -0700

clk: keystone: add Keystone PLL clock driver

Add the driver for the PLL IPs found on Keystone 2 devices. The PLL
IP typically has a multiplier, a divider and a post-divider. The PLL IPs like
ARMPLL, DDRPLL and PAPLL are controlled by the memory mapped register where
as the Main PLL is controlled by a PLL controller and memory map registers.

Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
Signed-off-by: Mike Turquette <mturquette@linaro.org>