amd64_edac: Cleanup DHAR handling
Adjust to F15h, simplify code, fixup macros.
Signed-off-by: Borislav Petkov <borislav.petkov@amd.com>
diff --git a/drivers/edac/amd64_edac.h b/drivers/edac/amd64_edac.h
index 93af357..a2bc9a6 100644
--- a/drivers/edac/amd64_edac.h
+++ b/drivers/edac/amd64_edac.h
@@ -175,20 +175,19 @@
#define dram_intlv_sel(pvt, i) ((pvt->ranges[i].lim.lo >> 8) & 0x7)
#define dram_dst_node(pvt, i) (pvt->ranges[i].lim.lo & 0x7)
-#define K8_DHAR 0xf0
-
+#define DHAR 0xf0
#define DHAR_VALID BIT(0)
-#define F10_DRAM_MEM_HOIST_VALID BIT(1)
+#define DRAM_MEM_HOIST_VALID BIT(1)
#define DHAR_BASE_MASK 0xff000000
-#define dhar_base(dhar) (dhar & DHAR_BASE_MASK)
+#define dhar_base(pvt) ((pvt)->dhar & DHAR_BASE_MASK)
#define K8_DHAR_OFFSET_MASK 0x0000ff00
-#define k8_dhar_offset(dhar) ((dhar & K8_DHAR_OFFSET_MASK) << 16)
+#define k8_dhar_offset(pvt) (((pvt)->dhar & K8_DHAR_OFFSET_MASK) << 16)
#define F10_DHAR_OFFSET_MASK 0x0000ff80
/* NOTE: Extra mask bit vs K8 */
-#define f10_dhar_offset(dhar) ((dhar & F10_DHAR_OFFSET_MASK) << 16)
+#define f10_dhar_offset(pvt) (((pvt)->dhar & F10_DHAR_OFFSET_MASK) << 16)
#define DCT_CFG_SEL 0x10C