pinctrl: qcom: Dynamic detection of tile bases

Previous implementation of hard coding the tile base of each GPIO in
the chip specific pinctrl driver introduces issues if different
versions of the chip introduces different tiles. Instead we should
dynamically detect the base of each GPIO by checking the status registers
for each base corresponding to that particular GPIO.

Change-Id: I6c15f5c5141019ed09d02361fb0b6c7eb7763308
Signed-off-by: Kyle Yan <kyan@codeaurora.org>
diff --git a/drivers/pinctrl/qcom/pinctrl-sdm845.c b/drivers/pinctrl/qcom/pinctrl-sdm845.c
index 7d125eb..31b4bc2 100644
--- a/drivers/pinctrl/qcom/pinctrl-sdm845.c
+++ b/drivers/pinctrl/qcom/pinctrl-sdm845.c
@@ -25,10 +25,8 @@
 		.ngroups = ARRAY_SIZE(fname##_groups),	\
 	}
 
-#define NORTH	0x00500000
-#define SOUTH	0x00900000
 #define REG_SIZE 0x1000
-#define PINGROUP(id, base, f1, f2, f3, f4, f5, f6, f7, f8, f9)	\
+#define PINGROUP(id, f1, f2, f3, f4, f5, f6, f7, f8, f9)	\
 	{						\
 		.name = "gpio" #id,			\
 		.pins = gpio##id##_pins,		\
@@ -46,11 +44,11 @@
 			msm_mux_##f9			\
 		},					\
 		.nfuncs = 10,				\
-		.ctl_reg = base + REG_SIZE * id,		\
-		.io_reg = base + 0x4 + REG_SIZE * id,		\
-		.intr_cfg_reg = base + 0x8 + REG_SIZE * id,	\
-		.intr_status_reg = base + 0xc + REG_SIZE * id,	\
-		.intr_target_reg = base + 0x8 + REG_SIZE * id,	\
+		.ctl_reg = REG_SIZE * id,		\
+		.io_reg = 0x4 + REG_SIZE * id,		\
+		.intr_cfg_reg = 0x8 + REG_SIZE * id,	\
+		.intr_status_reg = 0xc + REG_SIZE * id,	\
+		.intr_target_reg = 0x8 + REG_SIZE * id,	\
 		.mux_bit = 2,			\
 		.pull_bit = 0,			\
 		.drv_bit = 6,			\
@@ -116,6 +114,10 @@
 		.intr_detection_bit = -1,		\
 		.intr_detection_width = -1,		\
 	}
+
+static const u32 sdm845_tile_offsets[] = {0x500000, 0x900000};
+static u32 sdm845_pin_base[150];
+
 static const struct pinctrl_pin_desc sdm845_pins[] = {
 	PINCTRL_PIN(0, "GPIO_0"),
 	PINCTRL_PIN(1, "GPIO_1"),
@@ -2114,263 +2116,263 @@
 };
 
 static const struct msm_pingroup sdm845_groups[] = {
-	PINGROUP(0, NORTH, qup0, NA, reserved0, NA, NA, NA, NA, NA, NA),
-	PINGROUP(1, NORTH, qup0, NA, reserved1, NA, NA, NA, NA, NA, NA),
-	PINGROUP(2, NORTH, qup0, NA, reserved2, NA, NA, NA, NA, NA, NA),
-	PINGROUP(3, NORTH, qup0, NA, reserved3, NA, NA, NA, NA, NA, NA),
-	PINGROUP(4, NORTH, qup9, qdss_cti, reserved4, NA, NA, NA, NA, NA, NA),
-	PINGROUP(5, NORTH, qup9, qdss_cti, reserved5, NA, NA, NA, NA, NA, NA),
-	PINGROUP(6, NORTH, qup9, NA, ddr_pxi0, reserved6, NA, NA, NA, NA, NA),
-	PINGROUP(7, NORTH, qup9, ddr_bist, NA, atest_tsens2, vsense_trigger,
+	PINGROUP(0, qup0, NA, reserved0, NA, NA, NA, NA, NA, NA),
+	PINGROUP(1, qup0, NA, reserved1, NA, NA, NA, NA, NA, NA),
+	PINGROUP(2, qup0, NA, reserved2, NA, NA, NA, NA, NA, NA),
+	PINGROUP(3, qup0, NA, reserved3, NA, NA, NA, NA, NA, NA),
+	PINGROUP(4, qup9, qdss_cti, reserved4, NA, NA, NA, NA, NA, NA),
+	PINGROUP(5, qup9, qdss_cti, reserved5, NA, NA, NA, NA, NA, NA),
+	PINGROUP(6, qup9, NA, ddr_pxi0, reserved6, NA, NA, NA, NA, NA),
+	PINGROUP(7, qup9, ddr_bist, NA, atest_tsens2, vsense_trigger,
 		 atest_usb1, ddr_pxi0, reserved7, NA),
-	PINGROUP(8, NORTH, qup_l4, NA, ddr_bist, NA, NA, wlan1_adc1,
+	PINGROUP(8, qup_l4, NA, ddr_bist, NA, NA, wlan1_adc1,
 		 atest_usb13, ddr_pxi1, reserved8),
-	PINGROUP(9, NORTH, qup_l5, ddr_bist, NA, wlan1_adc0, atest_usb12,
+	PINGROUP(9, qup_l5, ddr_bist, NA, wlan1_adc0, atest_usb12,
 		 ddr_pxi1, reserved9, NA, NA),
-	PINGROUP(10, NORTH, mdp_vsync, qup_l6, ddr_bist, wlan2_adc1,
+	PINGROUP(10, mdp_vsync, qup_l6, ddr_bist, wlan2_adc1,
 		 atest_usb11, ddr_pxi2, reserved10, NA, NA),
-	PINGROUP(11, NORTH, mdp_vsync, edp_lcd, dbg_out, wlan2_adc0,
+	PINGROUP(11, mdp_vsync, edp_lcd, dbg_out, wlan2_adc0,
 		 atest_usb10, ddr_pxi2, reserved11, NA, NA),
-	PINGROUP(12, SOUTH, mdp_vsync, m_voc, tsif1_sync, ddr_pxi3, reserved12,
+	PINGROUP(12, mdp_vsync, m_voc, tsif1_sync, ddr_pxi3, reserved12,
 		 NA, NA, NA, NA),
-	PINGROUP(13, SOUTH, cam_mclk, pll_bypassnl, qdss_gpio0, ddr_pxi3,
+	PINGROUP(13, cam_mclk, pll_bypassnl, qdss_gpio0, ddr_pxi3,
 		 reserved13, NA, NA, NA, NA),
-	PINGROUP(14, SOUTH, cam_mclk, pll_reset, qdss_gpio1, reserved14, NA,
+	PINGROUP(14, cam_mclk, pll_reset, qdss_gpio1, reserved14, NA,
 		 NA, NA, NA, NA),
-	PINGROUP(15, SOUTH, cam_mclk, qdss_gpio2, reserved15, NA, NA, NA, NA,
+	PINGROUP(15, cam_mclk, qdss_gpio2, reserved15, NA, NA, NA, NA,
 		 NA, NA),
-	PINGROUP(16, SOUTH, cam_mclk, qdss_gpio3, reserved16, NA, NA, NA, NA,
+	PINGROUP(16, cam_mclk, qdss_gpio3, reserved16, NA, NA, NA, NA,
 		 NA, NA),
-	PINGROUP(17, SOUTH, cci_i2c, qup1, qdss_gpio4, reserved17, NA, NA, NA,
+	PINGROUP(17, cci_i2c, qup1, qdss_gpio4, reserved17, NA, NA, NA,
 		 NA, NA),
-	PINGROUP(18, SOUTH, cci_i2c, qup1, NA, qdss_gpio5, reserved18, NA, NA,
+	PINGROUP(18, cci_i2c, qup1, NA, qdss_gpio5, reserved18, NA, NA,
 		 NA, NA),
-	PINGROUP(19, SOUTH, cci_i2c, qup1, NA, qdss_gpio6, reserved19, NA, NA,
+	PINGROUP(19, cci_i2c, qup1, NA, qdss_gpio6, reserved19, NA, NA,
 		 NA, NA),
-	PINGROUP(20, SOUTH, cci_i2c, qup1, NA, qdss_gpio7, reserved20, NA, NA,
+	PINGROUP(20, cci_i2c, qup1, NA, qdss_gpio7, reserved20, NA, NA,
 		 NA, NA),
-	PINGROUP(21, SOUTH, cci_timer0, gcc_gp2, qdss_gpio8, reserved21, NA,
+	PINGROUP(21, cci_timer0, gcc_gp2, qdss_gpio8, reserved21, NA,
 		 NA, NA, NA, NA),
-	PINGROUP(22, SOUTH, cci_timer1, gcc_gp3, qdss_gpio, reserved22, NA, NA,
+	PINGROUP(22, cci_timer1, gcc_gp3, qdss_gpio, reserved22, NA, NA,
 		 NA, NA, NA),
-	PINGROUP(23, SOUTH, cci_timer2, qdss_gpio9, reserved23, NA, NA, NA, NA,
+	PINGROUP(23, cci_timer2, qdss_gpio9, reserved23, NA, NA, NA, NA,
 		 NA, NA),
-	PINGROUP(24, SOUTH, cci_timer3, cci_async, qdss_gpio10, reserved24, NA,
+	PINGROUP(24, cci_timer3, cci_async, qdss_gpio10, reserved24, NA,
 		 NA, NA, NA, NA),
-	PINGROUP(25, SOUTH, cci_timer4, cci_async, qdss_gpio11, reserved25, NA,
+	PINGROUP(25, cci_timer4, cci_async, qdss_gpio11, reserved25, NA,
 		 NA, NA, NA, NA),
-	PINGROUP(26, SOUTH, cci_async, qdss_gpio12, reserved26, NA, NA, NA, NA,
+	PINGROUP(26, cci_async, qdss_gpio12, reserved26, NA, NA, NA, NA,
 		 NA, NA),
-	PINGROUP(27, NORTH, qup2, qdss_gpio13, reserved27, NA, NA, NA, NA, NA,
+	PINGROUP(27, qup2, qdss_gpio13, reserved27, NA, NA, NA, NA, NA,
 		 NA),
-	PINGROUP(28, NORTH, qup2, qdss_gpio14, reserved28, NA, NA, NA, NA, NA,
+	PINGROUP(28, qup2, qdss_gpio14, reserved28, NA, NA, NA, NA, NA,
 		 NA),
-	PINGROUP(29, NORTH, qup2, NA, phase_flag1, qdss_gpio15, reserved29, NA,
+	PINGROUP(29, qup2, NA, phase_flag1, qdss_gpio15, reserved29, NA,
 		 NA, NA, NA),
-	PINGROUP(30, NORTH, qup2, phase_flag2, qdss_gpio, reserved30, NA, NA,
+	PINGROUP(30, qup2, phase_flag2, qdss_gpio, reserved30, NA, NA,
 		 NA, NA, NA),
-	PINGROUP(31, NORTH, qup11, qup14, reserved31, NA, NA, NA, NA, NA, NA),
-	PINGROUP(32, NORTH, qup11, qup14, NA, reserved32, NA, NA, NA, NA, NA),
-	PINGROUP(33, NORTH, qup11, qup14, NA, reserved33, NA, NA, NA, NA, NA),
-	PINGROUP(34, NORTH, qup11, qup14, NA, reserved34, NA, NA, NA, NA, NA),
-	PINGROUP(35, SOUTH, pci_e0, qup_l4, jitter_bist, NA, reserved35, NA,
+	PINGROUP(31, qup11, qup14, reserved31, NA, NA, NA, NA, NA, NA),
+	PINGROUP(32, qup11, qup14, NA, reserved32, NA, NA, NA, NA, NA),
+	PINGROUP(33, qup11, qup14, NA, reserved33, NA, NA, NA, NA, NA),
+	PINGROUP(34, qup11, qup14, NA, reserved34, NA, NA, NA, NA, NA),
+	PINGROUP(35, pci_e0, qup_l4, jitter_bist, NA, reserved35, NA,
 		 NA, NA, NA),
-	PINGROUP(36, SOUTH, pci_e0, qup_l5, pll_bist, NA, atest_tsens,
+	PINGROUP(36, pci_e0, qup_l5, pll_bist, NA, atest_tsens,
 		 reserved36, NA, NA, NA),
-	PINGROUP(37, SOUTH, qup_l6, agera_pll, NA, reserved37, NA, NA, NA, NA,
+	PINGROUP(37, qup_l6, agera_pll, NA, reserved37, NA, NA, NA, NA,
 		 NA),
-	PINGROUP(38, NORTH, usb_phy, NA, reserved38, NA, NA, NA, NA, NA, NA),
-	PINGROUP(39, NORTH, lpass_slimbus, NA, reserved39, NA, NA, NA, NA, NA,
+	PINGROUP(38, usb_phy, NA, reserved38, NA, NA, NA, NA, NA, NA),
+	PINGROUP(39, lpass_slimbus, NA, reserved39, NA, NA, NA, NA, NA,
 		 NA),
-	PINGROUP(40, SOUTH, sd_write, tsif1_error, NA, reserved40, NA, NA, NA,
+	PINGROUP(40, sd_write, tsif1_error, NA, reserved40, NA, NA, NA,
 		 NA, NA),
-	PINGROUP(41, SOUTH, qup3, NA, qdss_gpio6, reserved41, NA, NA, NA, NA,
+	PINGROUP(41, qup3, NA, qdss_gpio6, reserved41, NA, NA, NA, NA,
 		 NA),
-	PINGROUP(42, SOUTH, qup3, NA, qdss_gpio7, reserved42, NA, NA, NA, NA,
+	PINGROUP(42, qup3, NA, qdss_gpio7, reserved42, NA, NA, NA, NA,
 		 NA),
-	PINGROUP(43, SOUTH, qup3, NA, qdss_gpio14, reserved43, NA, NA, NA, NA,
+	PINGROUP(43, qup3, NA, qdss_gpio14, reserved43, NA, NA, NA, NA,
 		 NA),
-	PINGROUP(44, SOUTH, qup3, NA, qdss_gpio15, reserved44, NA, NA, NA, NA,
+	PINGROUP(44, qup3, NA, qdss_gpio15, reserved44, NA, NA, NA, NA,
 		 NA),
-	PINGROUP(45, NORTH, qup6, NA, reserved45, NA, NA, NA, NA, NA, NA),
-	PINGROUP(46, NORTH, qup6, NA, reserved46, NA, NA, NA, NA, NA, NA),
-	PINGROUP(47, NORTH, qup6, reserved47, NA, NA, NA, NA, NA, NA, NA),
-	PINGROUP(48, NORTH, qup6, reserved48, NA, NA, NA, NA, NA, NA, NA),
-	PINGROUP(49, NORTH, qup12, reserved49, NA, NA, NA, NA, NA, NA, NA),
-	PINGROUP(50, NORTH, qup12, reserved50, NA, NA, NA, NA, NA, NA, NA),
-	PINGROUP(51, NORTH, qup12, qdss_cti, reserved51, NA, NA, NA, NA, NA,
+	PINGROUP(45, qup6, NA, reserved45, NA, NA, NA, NA, NA, NA),
+	PINGROUP(46, qup6, NA, reserved46, NA, NA, NA, NA, NA, NA),
+	PINGROUP(47, qup6, reserved47, NA, NA, NA, NA, NA, NA, NA),
+	PINGROUP(48, qup6, reserved48, NA, NA, NA, NA, NA, NA, NA),
+	PINGROUP(49, qup12, reserved49, NA, NA, NA, NA, NA, NA, NA),
+	PINGROUP(50, qup12, reserved50, NA, NA, NA, NA, NA, NA, NA),
+	PINGROUP(51, qup12, qdss_cti, reserved51, NA, NA, NA, NA, NA,
 		 NA),
-	PINGROUP(52, NORTH, qup12, phase_flag16, qdss_cti, reserved52, NA, NA,
+	PINGROUP(52, qup12, phase_flag16, qdss_cti, reserved52, NA, NA,
 		 NA, NA, NA),
-	PINGROUP(53, NORTH, qup10, phase_flag11, reserved53, NA, NA, NA, NA,
+	PINGROUP(53, qup10, phase_flag11, reserved53, NA, NA, NA, NA,
 		 NA, NA),
-	PINGROUP(54, NORTH, qup10, NA, phase_flag12, reserved54, NA, NA, NA,
+	PINGROUP(54, qup10, NA, phase_flag12, reserved54, NA, NA, NA,
 		 NA, NA),
-	PINGROUP(55, NORTH, qup10, phase_flag13, reserved55, NA, NA, NA, NA,
+	PINGROUP(55, qup10, phase_flag13, reserved55, NA, NA, NA, NA,
 		 NA, NA),
-	PINGROUP(56, NORTH, qup10, phase_flag17, reserved56, NA, NA, NA, NA,
+	PINGROUP(56, qup10, phase_flag17, reserved56, NA, NA, NA, NA,
 		 NA, NA),
-	PINGROUP(57, NORTH, qua_mi2s, gcc_gp1, phase_flag18, reserved57, NA,
+	PINGROUP(57, qua_mi2s, gcc_gp1, phase_flag18, reserved57, NA,
 		 NA, NA, NA, NA),
-	PINGROUP(58, NORTH, qua_mi2s, gcc_gp2, phase_flag19, reserved58, NA,
+	PINGROUP(58, qua_mi2s, gcc_gp2, phase_flag19, reserved58, NA,
 		 NA, NA, NA, NA),
-	PINGROUP(59, NORTH, qua_mi2s, gcc_gp3, phase_flag20, reserved59, NA,
+	PINGROUP(59, qua_mi2s, gcc_gp3, phase_flag20, reserved59, NA,
 		 NA, NA, NA, NA),
-	PINGROUP(60, NORTH, qua_mi2s, cri_trng0, phase_flag21, reserved60, NA,
+	PINGROUP(60, qua_mi2s, cri_trng0, phase_flag21, reserved60, NA,
 		 NA, NA, NA, NA),
-	PINGROUP(61, NORTH, qua_mi2s, cri_trng1, phase_flag22, reserved61, NA,
+	PINGROUP(61, qua_mi2s, cri_trng1, phase_flag22, reserved61, NA,
 		 NA, NA, NA, NA),
-	PINGROUP(62, NORTH, qua_mi2s, cri_trng, phase_flag23, qdss_cti,
+	PINGROUP(62, qua_mi2s, cri_trng, phase_flag23, qdss_cti,
 		 reserved62, NA, NA, NA, NA),
-	PINGROUP(63, NORTH, qua_mi2s, NA, phase_flag24, qdss_cti, reserved63,
+	PINGROUP(63, qua_mi2s, NA, phase_flag24, qdss_cti, reserved63,
 		 NA, NA, NA, NA),
-	PINGROUP(64, NORTH, pri_mi2s, sp_cmu, phase_flag25, reserved64, NA, NA,
+	PINGROUP(64, pri_mi2s, sp_cmu, phase_flag25, reserved64, NA, NA,
 		 NA, NA, NA),
-	PINGROUP(65, NORTH, pri_mi2s, qup8, reserved65, NA, NA, NA, NA, NA, NA),
-	PINGROUP(66, NORTH, pri_mi2s_ws, qup8, reserved66, NA, NA, NA, NA, NA,
+	PINGROUP(65, pri_mi2s, qup8, reserved65, NA, NA, NA, NA, NA, NA),
+	PINGROUP(66, pri_mi2s_ws, qup8, reserved66, NA, NA, NA, NA, NA,
 		 NA),
-	PINGROUP(67, NORTH, pri_mi2s, qup8, reserved67, NA, NA, NA, NA, NA, NA),
-	PINGROUP(68, NORTH, pri_mi2s, qup8, reserved68, NA, NA, NA, NA, NA, NA),
-	PINGROUP(69, NORTH, spkr_i2s, audio_ref, reserved69, NA, NA, NA, NA,
+	PINGROUP(67, pri_mi2s, qup8, reserved67, NA, NA, NA, NA, NA, NA),
+	PINGROUP(68, pri_mi2s, qup8, reserved68, NA, NA, NA, NA, NA, NA),
+	PINGROUP(69, spkr_i2s, audio_ref, reserved69, NA, NA, NA, NA,
 		 NA, NA),
-	PINGROUP(70, NORTH, lpass_slimbus, spkr_i2s, reserved70, NA, NA, NA,
+	PINGROUP(70, lpass_slimbus, spkr_i2s, reserved70, NA, NA, NA,
 		 NA, NA, NA),
-	PINGROUP(71, NORTH, lpass_slimbus, spkr_i2s, tsense_pwm1, tsense_pwm2,
+	PINGROUP(71, lpass_slimbus, spkr_i2s, tsense_pwm1, tsense_pwm2,
 		 reserved71, NA, NA, NA, NA),
-	PINGROUP(72, NORTH, lpass_slimbus, spkr_i2s, reserved72, NA, NA, NA,
+	PINGROUP(72, lpass_slimbus, spkr_i2s, reserved72, NA, NA, NA,
 		 NA, NA, NA),
-	PINGROUP(73, NORTH, btfm_slimbus, atest_usb2, reserved73, NA, NA, NA,
+	PINGROUP(73, btfm_slimbus, atest_usb2, reserved73, NA, NA, NA,
 		 NA, NA, NA),
-	PINGROUP(74, NORTH, btfm_slimbus, ter_mi2s, phase_flag7, atest_usb23,
+	PINGROUP(74, btfm_slimbus, ter_mi2s, phase_flag7, atest_usb23,
 		 reserved74, NA, NA, NA, NA),
-	PINGROUP(75, NORTH, ter_mi2s, phase_flag8, qdss_gpio8, atest_usb22,
+	PINGROUP(75, ter_mi2s, phase_flag8, qdss_gpio8, atest_usb22,
 		 reserved75, NA, NA, NA, NA),
-	PINGROUP(76, NORTH, ter_mi2s, phase_flag9, qdss_gpio9, atest_usb21,
+	PINGROUP(76, ter_mi2s, phase_flag9, qdss_gpio9, atest_usb21,
 		 reserved76, NA, NA, NA, NA),
-	PINGROUP(77, NORTH, ter_mi2s, phase_flag4, qdss_gpio10, atest_usb20,
+	PINGROUP(77, ter_mi2s, phase_flag4, qdss_gpio10, atest_usb20,
 		 reserved77, NA, NA, NA, NA),
-	PINGROUP(78, NORTH, ter_mi2s, gcc_gp1, reserved78, NA, NA, NA, NA, NA,
+	PINGROUP(78, ter_mi2s, gcc_gp1, reserved78, NA, NA, NA, NA, NA,
 		 NA),
-	PINGROUP(79, NORTH, sec_mi2s, NA, NA, qdss_gpio11, reserved79, NA, NA,
+	PINGROUP(79, sec_mi2s, NA, NA, qdss_gpio11, reserved79, NA, NA,
 		 NA, NA),
-	PINGROUP(80, NORTH, sec_mi2s, NA, qdss_gpio12, reserved80, NA, NA, NA,
+	PINGROUP(80, sec_mi2s, NA, qdss_gpio12, reserved80, NA, NA, NA,
 		 NA, NA),
-	PINGROUP(81, NORTH, sec_mi2s, qup15, NA, reserved81, NA, NA, NA, NA,
+	PINGROUP(81, sec_mi2s, qup15, NA, reserved81, NA, NA, NA, NA,
 		 NA),
-	PINGROUP(82, NORTH, sec_mi2s, qup15, NA, reserved82, NA, NA, NA, NA,
+	PINGROUP(82, sec_mi2s, qup15, NA, reserved82, NA, NA, NA, NA,
 		 NA),
-	PINGROUP(83, NORTH, sec_mi2s, qup15, NA, reserved83, NA, NA, NA, NA,
+	PINGROUP(83, sec_mi2s, qup15, NA, reserved83, NA, NA, NA, NA,
 		 NA),
-	PINGROUP(84, NORTH, qup15, NA, reserved84, NA, NA, NA, NA, NA, NA),
-	PINGROUP(85, SOUTH, qup5, NA, reserved85, NA, NA, NA, NA, NA, NA),
-	PINGROUP(86, SOUTH, qup5, NA, NA, reserved86, NA, NA, NA, NA, NA),
-	PINGROUP(87, SOUTH, qup5, NA, reserved87, NA, NA, NA, NA, NA, NA),
-	PINGROUP(88, SOUTH, qup5, NA, reserved88, NA, NA, NA, NA, NA, NA),
-	PINGROUP(89, SOUTH, tsif1_clk, qup4, tgu_ch3, phase_flag10, reserved89,
+	PINGROUP(84, qup15, NA, reserved84, NA, NA, NA, NA, NA, NA),
+	PINGROUP(85, qup5, NA, reserved85, NA, NA, NA, NA, NA, NA),
+	PINGROUP(86, qup5, NA, NA, reserved86, NA, NA, NA, NA, NA),
+	PINGROUP(87, qup5, NA, reserved87, NA, NA, NA, NA, NA, NA),
+	PINGROUP(88, qup5, NA, reserved88, NA, NA, NA, NA, NA, NA),
+	PINGROUP(89, tsif1_clk, qup4, tgu_ch3, phase_flag10, reserved89,
 		 NA, NA, NA, NA),
-	PINGROUP(90, SOUTH, tsif1_en, mdp_vsync0, qup4, mdp_vsync1, mdp_vsync2,
+	PINGROUP(90, tsif1_en, mdp_vsync0, qup4, mdp_vsync1, mdp_vsync2,
 		 mdp_vsync3, tgu_ch0, phase_flag0, qdss_cti),
-	PINGROUP(91, SOUTH, tsif1_data, sdc4_cmd, qup4, tgu_ch1, NA, qdss_cti,
+	PINGROUP(91, tsif1_data, sdc4_cmd, qup4, tgu_ch1, NA, qdss_cti,
 		 reserved91, NA, NA),
-	PINGROUP(92, SOUTH, tsif2_error, sdc43, qup4, vfr_1, tgu_ch2, NA,
+	PINGROUP(92, tsif2_error, sdc43, qup4, vfr_1, tgu_ch2, NA,
 		 reserved92, NA, NA),
-	PINGROUP(93, SOUTH, tsif2_clk, sdc4_clk, qup7, NA, qdss_gpio13,
+	PINGROUP(93, tsif2_clk, sdc4_clk, qup7, NA, qdss_gpio13,
 		 reserved93, NA, NA, NA),
-	PINGROUP(94, SOUTH, tsif2_en, sdc42, qup7, NA, reserved94, NA, NA, NA,
+	PINGROUP(94, tsif2_en, sdc42, qup7, NA, reserved94, NA, NA, NA,
 		 NA),
-	PINGROUP(95, SOUTH, tsif2_data, sdc41, qup7, NA, NA, reserved95, NA,
+	PINGROUP(95, tsif2_data, sdc41, qup7, NA, NA, reserved95, NA,
 		 NA, NA),
-	PINGROUP(96, SOUTH, tsif2_sync, sdc40, qup7, phase_flag3, reserved96,
+	PINGROUP(96, tsif2_sync, sdc40, qup7, phase_flag3, reserved96,
 		 NA, NA, NA, NA),
-	PINGROUP(97, NORTH, NA, NA, mdp_vsync, ldo_en, reserved97, NA, NA, NA,
+	PINGROUP(97, NA, NA, mdp_vsync, ldo_en, reserved97, NA, NA, NA,
 		 NA),
-	PINGROUP(98, NORTH, NA, mdp_vsync, ldo_update, reserved98, NA, NA, NA,
+	PINGROUP(98, NA, mdp_vsync, ldo_update, reserved98, NA, NA, NA,
 		 NA, NA),
-	PINGROUP(99, NORTH, phase_flag14, reserved99, NA, NA, NA, NA, NA, NA,
+	PINGROUP(99, phase_flag14, reserved99, NA, NA, NA, NA, NA, NA,
 		 NA),
-	PINGROUP(100, NORTH, phase_flag15, reserved100, NA, NA, NA, NA, NA, NA,
+	PINGROUP(100, phase_flag15, reserved100, NA, NA, NA, NA, NA, NA,
 		 NA),
-	PINGROUP(101, NORTH, NA, reserved101, NA, NA, NA, NA, NA, NA, NA),
-	PINGROUP(102, NORTH, pci_e1, prng_rosc, reserved102, NA, NA, NA, NA,
+	PINGROUP(101, NA, reserved101, NA, NA, NA, NA, NA, NA, NA),
+	PINGROUP(102, pci_e1, prng_rosc, reserved102, NA, NA, NA, NA,
 		 NA, NA),
-	PINGROUP(103, NORTH, pci_e1, phase_flag5, reserved103, NA, NA, NA, NA,
+	PINGROUP(103, pci_e1, phase_flag5, reserved103, NA, NA, NA, NA,
 		 NA, NA),
-	PINGROUP(104, NORTH, NA, reserved104, NA, NA, NA, NA, NA, NA, NA),
-	PINGROUP(105, NORTH, uim2_data, qup13, qup_l4, NA, reserved105, NA, NA,
+	PINGROUP(104, NA, reserved104, NA, NA, NA, NA, NA, NA, NA),
+	PINGROUP(105, uim2_data, qup13, qup_l4, NA, reserved105, NA, NA,
 		 NA, NA),
-	PINGROUP(106, NORTH, uim2_clk, qup13, qup_l5, NA, reserved106, NA, NA,
+	PINGROUP(106, uim2_clk, qup13, qup_l5, NA, reserved106, NA, NA,
 		 NA, NA),
-	PINGROUP(107, NORTH, uim2_reset, qup13, qup_l6, reserved107, NA, NA,
+	PINGROUP(107, uim2_reset, qup13, qup_l6, reserved107, NA, NA,
 		 NA, NA, NA),
-	PINGROUP(108, NORTH, uim2_present, qup13, reserved108, NA, NA, NA, NA,
+	PINGROUP(108, uim2_present, qup13, reserved108, NA, NA, NA, NA,
 		 NA, NA),
-	PINGROUP(109, NORTH, uim1_data, reserved109, NA, NA, NA, NA, NA, NA,
+	PINGROUP(109, uim1_data, reserved109, NA, NA, NA, NA, NA, NA,
 		 NA),
-	PINGROUP(110, NORTH, uim1_clk, reserved110, NA, NA, NA, NA, NA, NA, NA),
-	PINGROUP(111, NORTH, uim1_reset, reserved111, NA, NA, NA, NA, NA, NA,
+	PINGROUP(110, uim1_clk, reserved110, NA, NA, NA, NA, NA, NA, NA),
+	PINGROUP(111, uim1_reset, reserved111, NA, NA, NA, NA, NA, NA,
 		 NA),
-	PINGROUP(112, NORTH, uim1_present, reserved112, NA, NA, NA, NA, NA, NA,
+	PINGROUP(112, uim1_present, reserved112, NA, NA, NA, NA, NA, NA,
 		 NA),
-	PINGROUP(113, NORTH, uim_batt, edp_hot, reserved113, NA, NA, NA, NA,
+	PINGROUP(113, uim_batt, edp_hot, reserved113, NA, NA, NA, NA,
 		 NA, NA),
-	PINGROUP(114, NORTH, NA, nav_pps, nav_pps, NA, NA, reserved114, NA, NA,
+	PINGROUP(114, NA, nav_pps, nav_pps, NA, NA, reserved114, NA, NA,
 		 NA),
-	PINGROUP(115, NORTH, NA, nav_pps, nav_pps, NA, NA, reserved115, NA, NA,
+	PINGROUP(115, NA, nav_pps, nav_pps, NA, NA, reserved115, NA, NA,
 		 NA),
-	PINGROUP(116, NORTH, NA, reserved116, NA, NA, NA, NA, NA, NA, NA),
-	PINGROUP(117, NORTH, NA, qdss_gpio0, atest_char, reserved117, NA, NA,
+	PINGROUP(116, NA, reserved116, NA, NA, NA, NA, NA, NA, NA),
+	PINGROUP(117, NA, qdss_gpio0, atest_char, reserved117, NA, NA,
 		 NA, NA, NA),
-	PINGROUP(118, NORTH, adsp_ext, NA, qdss_gpio1, atest_char3,
+	PINGROUP(118, adsp_ext, NA, qdss_gpio1, atest_char3,
 		 reserved118, NA, NA, NA, NA),
-	PINGROUP(119, NORTH, NA, qdss_gpio2, atest_char2, reserved119, NA, NA,
+	PINGROUP(119, NA, qdss_gpio2, atest_char2, reserved119, NA, NA,
 		 NA, NA, NA),
-	PINGROUP(120, NORTH, NA, qdss_gpio3, atest_char1, reserved120, NA, NA,
+	PINGROUP(120, NA, qdss_gpio3, atest_char1, reserved120, NA, NA,
 		 NA, NA, NA),
-	PINGROUP(121, NORTH, NA, qdss_gpio4, atest_char0, reserved121, NA, NA,
+	PINGROUP(121, NA, qdss_gpio4, atest_char0, reserved121, NA, NA,
 		 NA, NA, NA),
-	PINGROUP(122, NORTH, NA, qdss_gpio5, reserved122, NA, NA, NA, NA, NA,
+	PINGROUP(122, NA, qdss_gpio5, reserved122, NA, NA, NA, NA, NA,
 		 NA),
-	PINGROUP(123, NORTH, qup_l4, NA, qdss_gpio, reserved123, NA, NA, NA,
+	PINGROUP(123, qup_l4, NA, qdss_gpio, reserved123, NA, NA, NA,
 		 NA, NA),
-	PINGROUP(124, NORTH, qup_l5, NA, qdss_gpio, reserved124, NA, NA, NA,
+	PINGROUP(124, qup_l5, NA, qdss_gpio, reserved124, NA, NA, NA,
 		 NA, NA),
-	PINGROUP(125, NORTH, qup_l6, NA, reserved125, NA, NA, NA, NA, NA, NA),
-	PINGROUP(126, NORTH, NA, reserved126, NA, NA, NA, NA, NA, NA, NA),
-	PINGROUP(127, NORTH, NA, reserved127, NA, NA, NA, NA, NA, NA, NA),
-	PINGROUP(128, NORTH, nav_pps, nav_pps, NA, NA, reserved128, NA, NA, NA,
+	PINGROUP(125, qup_l6, NA, reserved125, NA, NA, NA, NA, NA, NA),
+	PINGROUP(126, NA, reserved126, NA, NA, NA, NA, NA, NA, NA),
+	PINGROUP(127, NA, reserved127, NA, NA, NA, NA, NA, NA, NA),
+	PINGROUP(128, nav_pps, nav_pps, NA, NA, reserved128, NA, NA, NA,
 		 NA),
-	PINGROUP(129, NORTH, nav_pps, nav_pps, NA, NA, reserved129, NA, NA, NA,
+	PINGROUP(129, nav_pps, nav_pps, NA, NA, reserved129, NA, NA, NA,
 		 NA),
-	PINGROUP(130, NORTH, qlink_request, NA, reserved130, NA, NA, NA, NA,
+	PINGROUP(130, qlink_request, NA, reserved130, NA, NA, NA, NA,
 		 NA, NA),
-	PINGROUP(131, NORTH, qlink_enable, NA, reserved131, NA, NA, NA, NA, NA,
+	PINGROUP(131, qlink_enable, NA, reserved131, NA, NA, NA, NA, NA,
 		 NA),
-	PINGROUP(132, NORTH, NA, NA, reserved132, NA, NA, NA, NA, NA, NA),
-	PINGROUP(133, NORTH, NA, reserved133, NA, NA, NA, NA, NA, NA, NA),
-	PINGROUP(134, NORTH, NA, reserved134, NA, NA, NA, NA, NA, NA, NA),
-	PINGROUP(135, NORTH, NA, pa_indicator, NA, reserved135, NA, NA, NA, NA,
+	PINGROUP(132, NA, NA, reserved132, NA, NA, NA, NA, NA, NA),
+	PINGROUP(133, NA, reserved133, NA, NA, NA, NA, NA, NA, NA),
+	PINGROUP(134, NA, reserved134, NA, NA, NA, NA, NA, NA, NA),
+	PINGROUP(135, NA, pa_indicator, NA, reserved135, NA, NA, NA, NA,
 		 NA),
-	PINGROUP(136, NORTH, NA, reserved136, NA, NA, NA, NA, NA, NA, NA),
-	PINGROUP(137, NORTH, NA, NA, phase_flag26, reserved137, NA, NA, NA, NA,
+	PINGROUP(136, NA, reserved136, NA, NA, NA, NA, NA, NA, NA),
+	PINGROUP(137, NA, NA, phase_flag26, reserved137, NA, NA, NA, NA,
 		 NA),
-	PINGROUP(138, NORTH, NA, NA, phase_flag27, reserved138, NA, NA, NA, NA,
+	PINGROUP(138, NA, NA, phase_flag27, reserved138, NA, NA, NA, NA,
 		 NA),
-	PINGROUP(139, NORTH, NA, phase_flag28, reserved139, NA, NA, NA, NA, NA,
+	PINGROUP(139, NA, phase_flag28, reserved139, NA, NA, NA, NA, NA,
 		 NA),
-	PINGROUP(140, NORTH, NA, NA, phase_flag6, reserved140, NA, NA, NA, NA,
+	PINGROUP(140, NA, NA, phase_flag6, reserved140, NA, NA, NA, NA,
 		 NA),
-	PINGROUP(141, NORTH, NA, phase_flag29, reserved141, NA, NA, NA, NA, NA,
+	PINGROUP(141, NA, phase_flag29, reserved141, NA, NA, NA, NA, NA,
 		 NA),
-	PINGROUP(142, NORTH, NA, phase_flag30, reserved142, NA, NA, NA, NA, NA,
+	PINGROUP(142, NA, phase_flag30, reserved142, NA, NA, NA, NA, NA,
 		 NA),
-	PINGROUP(143, NORTH, NA, nav_pps, nav_pps, NA, phase_flag31,
+	PINGROUP(143, NA, nav_pps, nav_pps, NA, phase_flag31,
 		 reserved143, NA, NA, NA),
-	PINGROUP(144, NORTH, mss_lte, reserved144, NA, NA, NA, NA, NA, NA, NA),
-	PINGROUP(145, NORTH, mss_lte, NA, reserved145, NA, NA, NA, NA, NA, NA),
-	PINGROUP(146, NORTH, NA, NA, reserved146, NA, NA, NA, NA, NA, NA),
-	PINGROUP(147, NORTH, NA, NA, reserved147, NA, NA, NA, NA, NA, NA),
-	PINGROUP(148, NORTH, NA, reserved148, NA, NA, NA, NA, NA, NA, NA),
-	PINGROUP(149, NORTH, NA, reserved149, NA, NA, NA, NA, NA, NA, NA),
+	PINGROUP(144, mss_lte, reserved144, NA, NA, NA, NA, NA, NA, NA),
+	PINGROUP(145, mss_lte, NA, reserved145, NA, NA, NA, NA, NA, NA),
+	PINGROUP(146, NA, NA, reserved146, NA, NA, NA, NA, NA, NA),
+	PINGROUP(147, NA, NA, reserved147, NA, NA, NA, NA, NA, NA),
+	PINGROUP(148, NA, reserved148, NA, NA, NA, NA, NA, NA, NA),
+	PINGROUP(149, NA, reserved149, NA, NA, NA, NA, NA, NA, NA),
 	SDC_QDSD_PINGROUP(sdc2_clk, 0x99a000, 14, 6),
 	SDC_QDSD_PINGROUP(sdc2_cmd, 0x99a000, 11, 3),
 	SDC_QDSD_PINGROUP(sdc2_data, 0x99a000, 9, 0),
@@ -2465,6 +2467,10 @@
 	.ngpios = 150,
 	.dir_conn = sdm845_dir_conn,
 	.n_dir_conns = ARRAY_SIZE(sdm845_dir_conn),
+	.tile_offsets = sdm845_tile_offsets,
+	.n_tile_offsets = ARRAY_SIZE(sdm845_tile_offsets),
+	.pin_base = sdm845_pin_base,
+	.reg_size = REG_SIZE,
 };
 
 static int sdm845_pinctrl_probe(struct platform_device *pdev)