| commit | 35399dda011b515120e0c39463ac32f0cac75c6a | [log] [tgz] |
|---|---|---|
| author | Andrew Bresticker <abrestic@chromium.org> | Wed Sep 25 14:12:49 2013 -0700 |
| committer | Tomasz Figa <t.figa@samsung.com> | Wed Jan 08 18:02:42 2014 +0100 |
| tree | d3117a0bf64baa1b1841570ed61af2cbd25f3cf0 | |
| parent | 547f33509ccc6e016df02600d377778b75e26a7b [diff] |
clk: exynos5250: add clock ID for div_pcm0 There is no gate for the PCM clock input to the AudioSS block, so the parent of sclk_pcm is div_pcm0. Add a clock ID for it so that we can reference it in device trees. Signed-off-by: Andrew Bresticker <abrestic@chromium.org> Reviewed-by: Tomasz Figa <t.figa@samsung.com> Acked-by: Mike Turquette <mturquette@linaro.org> Acked-by: Kukjin Kim <kgene.kim@samsung.com> Signed-off-by: Tomasz Figa <t.figa@samsung.com>