drm/i915: Move Braswell stop_machine GGTT insertion workaround
There was a silent conflict between
commit 0a878716265e9af9f697264dc2e858fcc060d833
Author: Daniel Vetter <daniel.vetter@ffwll.ch>
Date: Thu Oct 15 14:23:01 2015 +0200
drm/i915: restore ggtt double-bind avoidance
and
commit 5bab6f60cb4d1417ad7c599166bcfec87529c1a2
Author: Chris Wilson <chris@chris-wilson.co.uk>
Date: Fri Oct 23 18:43:32 2015 +0100
drm/i915: Serialise updates to GGTT with access through GGTT on Braswell
thankfully caught by the extra WARN safegaurd in 0a878716. Since we now
override the GGTT insert_pages callback when installing the aliasing
ppgtt, we assert that the callback is the original ggtt routine.
However, on Braswell we now use a different insertion routine to
serialise access through the GGTT with updating the PTE and hence the
conflict. To avoid the conflict, move the custom insertion routine for
Braswell down a level.
Reported-by: Ville Syrjälä <ville.syrjala@linux.intel.com
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Ville Syrjälä <ville.syrjala@linux.intel.com
Cc: Daniel Vetter <daniel.vetter@ffwll.ch>
Cc: Michel Thierry <michel.thierry@intel.com>
Cc: Mika Kuoppala <mika.kuoppala@intel.com>
Link: http://patchwork.freedesktop.org/patch/msgid/1447859979-20107-1-git-send-email-chris@chris-wilson.co.uk
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Tested-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Cc: drm-intel-fixes@lists.freedesktop.org
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c b/drivers/gpu/drm/i915/i915_gem_gtt.c
index 52bc6c3..56f4f2e 100644
--- a/drivers/gpu/drm/i915/i915_gem_gtt.c
+++ b/drivers/gpu/drm/i915/i915_gem_gtt.c
@@ -2384,6 +2384,32 @@
assert_rpm_atomic_end(dev_priv, rpm_atomic_seq);
}
+struct insert_entries {
+ struct i915_address_space *vm;
+ struct sg_table *st;
+ uint64_t start;
+ enum i915_cache_level level;
+ u32 flags;
+};
+
+static int gen8_ggtt_insert_entries__cb(void *_arg)
+{
+ struct insert_entries *arg = _arg;
+ gen8_ggtt_insert_entries(arg->vm, arg->st,
+ arg->start, arg->level, arg->flags);
+ return 0;
+}
+
+static void gen8_ggtt_insert_entries__BKL(struct i915_address_space *vm,
+ struct sg_table *st,
+ uint64_t start,
+ enum i915_cache_level level,
+ u32 flags)
+{
+ struct insert_entries arg = { vm, st, start, level, flags };
+ stop_machine(gen8_ggtt_insert_entries__cb, &arg, NULL);
+}
+
/*
* Binds an object into the global gtt with the specified cache level. The object
* will be accessible to the GPU via commands whose operands reference offsets
@@ -2560,26 +2586,6 @@
return 0;
}
-struct ggtt_bind_vma__cb {
- struct i915_vma *vma;
- enum i915_cache_level cache_level;
- u32 flags;
-};
-
-static int ggtt_bind_vma__cb(void *_arg)
-{
- struct ggtt_bind_vma__cb *arg = _arg;
- return ggtt_bind_vma(arg->vma, arg->cache_level, arg->flags);
-}
-
-static int ggtt_bind_vma__BKL(struct i915_vma *vma,
- enum i915_cache_level cache_level,
- u32 flags)
-{
- struct ggtt_bind_vma__cb arg = { vma, cache_level, flags };
- return stop_machine(ggtt_bind_vma__cb, &arg, NULL);
-}
-
static int aliasing_gtt_bind_vma(struct i915_vma *vma,
enum i915_cache_level cache_level,
u32 flags)
@@ -3048,8 +3054,8 @@
dev_priv->gtt.base.bind_vma = ggtt_bind_vma;
dev_priv->gtt.base.unbind_vma = ggtt_unbind_vma;
- if (IS_CHERRYVIEW(dev))
- dev_priv->gtt.base.bind_vma = ggtt_bind_vma__BKL;
+ if (IS_CHERRYVIEW(dev_priv))
+ dev_priv->gtt.base.insert_entries = gen8_ggtt_insert_entries__BKL;
return ret;
}