tree 87012dc0f962eab0f2d9ec36d0c5592d68d849e4
parent a7dae1551b55eff5308e5aa0e0149e57533ecb50
author Murali Karicheri <m-karicheri2@ti.com> 1432915453 -0400
committer Olof Johansson <olof@lixom.net> 1438374611 +0200

ARM: dts: keystone: fix dt bindings to use post div register for mainpll

All of the keystone devices have a separate register to hold post
divider value for main pll clock. Currently the fixed-postdiv
value used for k2hk/l/e SoCs works by sheer luck as u-boot happens to
use a value of 2 for this. Now that we have fixed this in the pll
clock driver change the dt bindings for the same.

Signed-off-by: Murali Karicheri <m-karicheri2@ti.com>
Acked-by: Santosh Shilimkar <ssantosh@kernel.org>
Signed-off-by: Olof Johansson <olof@lixom.net>