| commit | c44b56af9ca3a6f135d8f22b9a240f53909b371e | [log] [tgz] |
|---|---|---|
| author | Nicolin Chen <Guangyu.Chen@freescale.com> | Wed Jul 23 19:23:39 2014 +0800 |
| committer | Mark Brown <broonie@linaro.org> | Fri Jul 25 18:52:35 2014 +0100 |
| tree | 2f21074e058c08f5eb37b4993dfee8096927967a | |
| parent | f4075a8f452aff5465c6522c92da9db71ed11b7f [diff] |
ASoC: fsl_sai: Don't reset FIFO until TE/RE bit is unset TE/RE bit of T/RCSR will remain set untill the current frame is physically finished. The FIFO reset operation should wait this bit's totally cleared rather than ignoring its status which might cause TE/RE disabling failed. This patch adds delay and timeout to wait for its completion before FIFO reset. Signed-off-by: Nicolin Chen <nicoleotsuka@gmail.com> Signed-off-by: Mark Brown <broonie@linaro.org>