mmc: SDHC 3.0: Base clock frequency change in spec 3.0
SDHC Spec 3.0: Capabilities Register bits[15-08] are Base Clock Frequency
1.0/2.0: Capabilities Register bits[13-08] are Base Clock Frequency
Signed-off-by: Zhangfei Gao <zgao6@marvell.com>
Cc: David Vrabel <david.vrabel@csr.com>
Cc: Matt Fleming <matt@console-pimps.org>
Cc: Michal Miroslaw <mirqus@gmail.com>
Signed-off-by: Andrew Morton <akpm@linux-foundation.org>
Signed-off-by: Chris Ball <cjb@laptop.org>
diff --git a/drivers/mmc/host/sdhci.h b/drivers/mmc/host/sdhci.h
index 950d4fd..ae28a31 100644
--- a/drivers/mmc/host/sdhci.h
+++ b/drivers/mmc/host/sdhci.h
@@ -144,6 +144,7 @@
#define SDHCI_TIMEOUT_CLK_SHIFT 0
#define SDHCI_TIMEOUT_CLK_UNIT 0x00000080
#define SDHCI_CLOCK_BASE_MASK 0x00003F00
+#define SDHCI_CLOCK_V3_BASE_MASK 0x0000FF00
#define SDHCI_CLOCK_BASE_SHIFT 8
#define SDHCI_MAX_BLOCK_MASK 0x00030000
#define SDHCI_MAX_BLOCK_SHIFT 16