tree 4563578a985b1ceb09e067c76936510eeac6d4e8
parent f684362689ddc4a4e055be438d6416cc280a1372
author Maciej W. Rozycki <macro@linux-mips.org> 1428100053 +0100
committer Ralf Baechle <ralf@linux-mips.org> 1428448228 +0200

MIPS: math-emu: Implement the FCCR, FEXR and FENR registers

Implement the FCCR, FEXR and FENR "shadow" FPU registers for the
architecture levels that include them, for the CFC1 and CTC1
instructions in the full emulation mode.

For completeness add macros for the CP1 UFR and UNFR registers too, no
actual implementation though.

Signed-off-by: Maciej W. Rozycki <macro@linux-mips.org>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/9708/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>