Merge branch 'msm-next' of git://people.freedesktop.org/~robclark/linux into drm-next
1) add LVDS support for mdp4 (tested with auo B101XTN01.0 panel)
2) add B101XTN01.0 panel
3) bit of gpu refactoring to prepare for addition of addition gpu
generations beyond just a3xx
* 'msm-next' of git://people.freedesktop.org/~robclark/linux:
drm/msm/adreno: push dump/show stuff to base class
drm/msm/adreno: bit of init refactoring
drm/msm/adreno: move decision about what gpu to to load
drm/msm/adreno: split adreno device out into it's own file
drm/panel/simple: add optronics B101XTN01.0 (v3)
drm/msm/mdp4: add LVDS panel support
drm/msm/mdp4: fix blend setup with multiple crtcs
drm/msm: update generated headers
diff --git a/drivers/gpu/drm/radeon/radeon_object.c b/drivers/gpu/drm/radeon/radeon_object.c
index aadbd36..8abee5f 100644
--- a/drivers/gpu/drm/radeon/radeon_object.c
+++ b/drivers/gpu/drm/radeon/radeon_object.c
@@ -144,7 +144,12 @@
for (i = 0; i < c; ++i) {
rbo->placements[i].fpfn = 0;
- rbo->placements[i].lpfn = 0;
+ if ((rbo->flags & RADEON_GEM_CPU_ACCESS) &&
+ (rbo->placements[i].flags & TTM_PL_FLAG_VRAM))
+ rbo->placements[i].lpfn =
+ rbo->rdev->mc.visible_vram_size >> PAGE_SHIFT;
+ else
+ rbo->placements[i].lpfn = 0;
}
/*
@@ -152,7 +157,9 @@
* improve fragmentation quality.
* 512kb was measured as the most optimal number.
*/
- if (rbo->tbo.mem.size > 512 * 1024) {
+ if (!((rbo->flags & RADEON_GEM_CPU_ACCESS) &&
+ (rbo->placements[i].flags & TTM_PL_FLAG_VRAM)) &&
+ rbo->tbo.mem.size > 512 * 1024) {
for (i = 0; i < c; i++) {
rbo->placements[i].flags |= TTM_PL_FLAG_TOPDOWN;
}
@@ -304,18 +311,15 @@
}
radeon_ttm_placement_from_domain(bo, domain);
for (i = 0; i < bo->placement.num_placement; i++) {
- unsigned lpfn = 0;
-
/* force to pin into visible video ram */
- if (bo->placements[i].flags & TTM_PL_FLAG_VRAM)
- lpfn = bo->rdev->mc.visible_vram_size >> PAGE_SHIFT;
+ if ((bo->placements[i].flags & TTM_PL_FLAG_VRAM) &&
+ !(bo->flags & RADEON_GEM_NO_CPU_ACCESS) &&
+ (!max_offset || max_offset > bo->rdev->mc.visible_vram_size))
+ bo->placements[i].lpfn =
+ bo->rdev->mc.visible_vram_size >> PAGE_SHIFT;
else
- lpfn = bo->rdev->mc.gtt_size >> PAGE_SHIFT; /* ??? */
+ bo->placements[i].lpfn = max_offset >> PAGE_SHIFT;
- if (max_offset)
- lpfn = min (lpfn, (unsigned)(max_offset >> PAGE_SHIFT));
-
- bo->placements[i].lpfn = lpfn;
bo->placements[i].flags |= TTM_PL_FLAG_NO_EVICT;
}
diff --git a/include/uapi/drm/radeon_drm.h b/include/uapi/drm/radeon_drm.h
index 375b6e6..50d0fb4 100644
--- a/include/uapi/drm/radeon_drm.h
+++ b/include/uapi/drm/radeon_drm.h
@@ -801,6 +801,10 @@
#define RADEON_GEM_NO_BACKING_STORE (1 << 0)
#define RADEON_GEM_GTT_UC (1 << 1)
#define RADEON_GEM_GTT_WC (1 << 2)
+/* BO is expected to be accessed by the CPU */
+#define RADEON_GEM_CPU_ACCESS (1 << 3)
+/* CPU access is not expected to work for this BO */
+#define RADEON_GEM_NO_CPU_ACCESS (1 << 4)
struct drm_radeon_gem_create {
uint64_t size;