| commit | c520abadbc56a2740021910d2c6412f826a10059 | [log] [tgz] |
|---|---|---|
| author | Bob Moore <robert.moore@intel.com> | Wed Feb 18 14:20:12 2009 +0800 |
| committer | Len Brown <len.brown@intel.com> | Thu Mar 26 16:38:24 2009 -0400 |
| tree | bb491ead1a13afcf759d42e29175c5391449661c | |
| parent | d3319d1717a250e92be66a487dc3e0429112c284 [diff] |
ACPICA: Fix writes to optional PM1B registers On read, shift B register bits above the A bits. On write, shift B bits down to zero before writing the B register. New: acpi_hw_read_multiple, acpi_hw_write_multiple. These two functions now transparently handle the (possible) split registers for PM1 Status, Enable, and Control. Signed-off-by: Bob Moore <robert.moore@intel.com> Signed-off-by: Lin Ming <ming.m.lin@intel.com> Signed-off-by: Len Brown <len.brown@intel.com>