tree bb491ead1a13afcf759d42e29175c5391449661c
parent d3319d1717a250e92be66a487dc3e0429112c284
author Bob Moore <robert.moore@intel.com> 1234938012 +0800
committer Len Brown <len.brown@intel.com> 1238099904 -0400

ACPICA: Fix writes to optional PM1B registers

On read, shift B register bits above the A bits. On write,
shift B bits down to zero before writing the B register. New:
acpi_hw_read_multiple, acpi_hw_write_multiple. These two functions now
transparently handle the (possible) split registers for PM1 Status,
Enable, and Control.

Signed-off-by: Bob Moore <robert.moore@intel.com>
Signed-off-by: Lin Ming <ming.m.lin@intel.com>
Signed-off-by: Len Brown <len.brown@intel.com>