| commit | c66c1d79a94a7a302e2dc6c93da40902423eac3e | [log] [tgz] |
|---|---|---|
| author | Paul Mundt <lethal@linux-sh.org> | Fri Apr 17 16:38:00 2009 +0900 |
| committer | Paul Mundt <lethal@linux-sh.org> | Fri Apr 17 16:38:00 2009 +0900 |
| tree | e29bf59d813f623b3a71f5ccb2d0f8ac16fec051 | |
| parent | ab78cbcf6877334fc20868b7df7887349e2e01c8 [diff] |
sh: pci: Set pci_cache_line_size on SH7780 via the PCICLS register. The SH7780 PCIC contains a read-only cache line size register that we can derive pci_cache_line_size from. So, make sure that the software idea of the cache line size actually matches the host controller's idea. Signed-off-by: Paul Mundt <lethal@linux-sh.org>