drm/msm/sde: Move DSPP/SSPP color process to one location
The color processing blocks for SSPP and DSPP share the same register
programming sequences. This change moves the current DSPP and SSPP
functionality to a common location and uses the helper function for
common code.
Change-Id: I0f41453a977ba2d3b4ce12cc622706619c48280c
Signed-off-by: Benet Clark <benetc@codeaurora.org>
diff --git a/drivers/gpu/drm/msm/sde/sde_hw_color_processing_v1_7.c b/drivers/gpu/drm/msm/sde/sde_hw_color_processing_v1_7.c
index 47c9bd9..f1f66f3 100644
--- a/drivers/gpu/drm/msm/sde/sde_hw_color_processing_v1_7.c
+++ b/drivers/gpu/drm/msm/sde/sde_hw_color_processing_v1_7.c
@@ -13,13 +13,22 @@
#include <drm/msm_drm_pp.h>
#include "sde_hw_color_processing_v1_7.h"
-#define PA_HUE_OFF 0x110
+#define PA_HUE_VIG_OFF 0x110
+#define PA_SAT_VIG_OFF 0x114
+#define PA_VAL_VIG_OFF 0x118
+#define PA_CONT_VIG_OFF 0x11C
+
+#define PA_HUE_DSPP_OFF 0x238
+#define PA_SAT_DSPP_OFF 0x23C
+#define PA_VAL_DSPP_OFF 0x240
+#define PA_CONT_DSPP_OFF 0x244
+
+#define PA_LUTV_DSPP_OFF 0x1400
+#define PA_LUT_SWAP_OFF 0x234
+
#define PA_HUE_MASK 0xFFF
-#define PA_SAT_OFF 0x114
#define PA_SAT_MASK 0xFFFF
-#define PA_VAL_OFF 0x118
#define PA_VAL_MASK 0xFF
-#define PA_CONT_OFF 0x11C
#define PA_CONT_MASK 0xFF
#define MEMCOL_PWL0_OFF 0x88
@@ -48,94 +57,203 @@
#define VIG_OP_PA_VAL_EN BIT(27)
#define VIG_OP_PA_CONT_EN BIT(28)
-#define PA_DISABLE_REQUIRED(x) !((x) & \
- (VIG_OP_PA_SKIN_EN | VIG_OP_PA_SKY_EN | \
- VIG_OP_PA_FOL_EN | VIG_OP_PA_HUE_EN | \
- VIG_OP_PA_SAT_EN | VIG_OP_PA_VAL_EN | \
- VIG_OP_PA_CONT_EN))
+#define DSPP_OP_SZ_VAL_EN BIT(31)
+#define DSPP_OP_SZ_SAT_EN BIT(30)
+#define DSPP_OP_SZ_HUE_EN BIT(29)
+#define DSPP_OP_PA_HUE_EN BIT(25)
+#define DSPP_OP_PA_SAT_EN BIT(26)
+#define DSPP_OP_PA_VAL_EN BIT(27)
+#define DSPP_OP_PA_CONT_EN BIT(28)
+#define DSPP_OP_PA_EN BIT(20)
+#define DSPP_OP_PA_LUTV_EN BIT(19)
+#define DSPP_OP_PA_SKIN_EN BIT(5)
+#define DSPP_OP_PA_FOL_EN BIT(6)
+#define DSPP_OP_PA_SKY_EN BIT(7)
+
+#define REG_MASK(n) ((BIT(n)) - 1)
+
+#define PA_VIG_DISABLE_REQUIRED(x) \
+ !((x) & (VIG_OP_PA_SKIN_EN | VIG_OP_PA_SKY_EN | \
+ VIG_OP_PA_FOL_EN | VIG_OP_PA_HUE_EN | \
+ VIG_OP_PA_SAT_EN | VIG_OP_PA_VAL_EN | \
+ VIG_OP_PA_CONT_EN))
+
+
+#define PA_DSPP_DISABLE_REQUIRED(x) \
+ !((x) & (DSPP_OP_PA_SKIN_EN | DSPP_OP_PA_SKY_EN | \
+ DSPP_OP_PA_FOL_EN | DSPP_OP_PA_HUE_EN | \
+ DSPP_OP_PA_SAT_EN | DSPP_OP_PA_VAL_EN | \
+ DSPP_OP_PA_CONT_EN | DSPP_OP_PA_LUTV_EN))
+
+#define DSPP_OP_PCC_ENABLE BIT(0)
+#define PCC_OP_MODE_OFF 0
+#define PCC_CONST_COEFF_OFF 4
+#define PCC_R_COEFF_OFF 0x10
+#define PCC_G_COEFF_OFF 0x1C
+#define PCC_B_COEFF_OFF 0x28
+#define PCC_RG_COEFF_OFF 0x34
+#define PCC_RB_COEFF_OFF 0x40
+#define PCC_GB_COEFF_OFF 0x4C
+#define PCC_RGB_COEFF_OFF 0x58
+#define PCC_CONST_COEFF_MASK 0xFFFF
+#define PCC_COEFF_MASK 0x3FFFF
+
+#define SSPP 0
+#define DSPP 1
+
+static void __setup_pa_hue(struct sde_hw_blk_reg_map *hw,
+ const struct sde_pp_blk *blk, uint32_t hue,
+ int location)
+{
+ u32 base = blk->base;
+ u32 offset = (location == DSPP) ? PA_HUE_DSPP_OFF : PA_HUE_VIG_OFF;
+ u32 op_hue_en = (location == DSPP) ? DSPP_OP_PA_HUE_EN :
+ VIG_OP_PA_HUE_EN;
+ u32 op_pa_en = (location == DSPP) ? DSPP_OP_PA_EN : VIG_OP_PA_EN;
+ u32 disable_req;
+ u32 opmode;
+
+ SDE_REG_WRITE(hw, base + offset, hue & PA_HUE_MASK);
+
+ opmode = SDE_REG_READ(hw, base);
+
+ if (!hue) {
+ opmode &= ~op_hue_en;
+ disable_req = (location == DSPP) ?
+ PA_DSPP_DISABLE_REQUIRED(opmode) :
+ PA_VIG_DISABLE_REQUIRED(opmode);
+ if (disable_req)
+ opmode &= ~op_pa_en;
+ } else {
+ opmode |= op_hue_en | op_pa_en;
+ }
+
+ SDE_REG_WRITE(hw, base, opmode);
+}
void sde_setup_pipe_pa_hue_v1_7(struct sde_hw_pipe *ctx, void *cfg)
{
uint32_t hue = *((uint32_t *)cfg);
- u32 base = ctx->cap->sblk->hsic_blk.base;
- u32 opmode = 0;
- SDE_REG_WRITE(&ctx->hw, base + PA_HUE_OFF, hue & PA_HUE_MASK);
+ __setup_pa_hue(&ctx->hw, &ctx->cap->sblk->hsic_blk, hue, SSPP);
+}
- opmode = SDE_REG_READ(&ctx->hw, base);
+void sde_setup_dspp_pa_hue_v1_7(struct sde_hw_dspp *ctx, void *cfg)
+{
+ uint32_t hue = *((uint32_t *)cfg);
- if (!hue) {
- opmode &= ~VIG_OP_PA_HUE_EN;
- if (PA_DISABLE_REQUIRED(opmode))
- opmode &= ~VIG_OP_PA_EN;
+ __setup_pa_hue(&ctx->hw, &ctx->cap->sblk->hsic, hue, DSPP);
+}
+
+static void __setup_pa_sat(struct sde_hw_blk_reg_map *hw,
+ const struct sde_pp_blk *blk, uint32_t sat,
+ int location)
+{
+ u32 base = blk->base;
+ u32 offset = (location == DSPP) ? PA_SAT_DSPP_OFF : PA_SAT_VIG_OFF;
+ u32 op_sat_en = (location == DSPP) ?
+ DSPP_OP_PA_SAT_EN : VIG_OP_PA_SAT_EN;
+ u32 op_pa_en = (location == DSPP) ? DSPP_OP_PA_EN : VIG_OP_PA_EN;
+ u32 disable_req;
+ u32 opmode;
+
+ SDE_REG_WRITE(hw, base + offset, sat & PA_SAT_MASK);
+
+ opmode = SDE_REG_READ(hw, base);
+
+ if (!sat) {
+ opmode &= ~op_sat_en;
+ disable_req = (location == DSPP) ?
+ PA_DSPP_DISABLE_REQUIRED(opmode) :
+ PA_VIG_DISABLE_REQUIRED(opmode);
+ if (disable_req)
+ opmode &= ~op_pa_en;
} else {
- opmode |= VIG_OP_PA_HUE_EN | VIG_OP_PA_EN;
+ opmode |= op_sat_en | op_pa_en;
}
- SDE_REG_WRITE(&ctx->hw, base, opmode);
+ SDE_REG_WRITE(hw, base, opmode);
}
void sde_setup_pipe_pa_sat_v1_7(struct sde_hw_pipe *ctx, void *cfg)
{
uint32_t sat = *((uint32_t *)cfg);
- u32 base = ctx->cap->sblk->hsic_blk.base;
- u32 opmode = 0;
- SDE_REG_WRITE(&ctx->hw, base + PA_SAT_OFF, sat & PA_SAT_MASK);
+ __setup_pa_sat(&ctx->hw, &ctx->cap->sblk->hsic_blk, sat, SSPP);
+}
- opmode = SDE_REG_READ(&ctx->hw, base);
+static void __setup_pa_val(struct sde_hw_blk_reg_map *hw,
+ const struct sde_pp_blk *blk, uint32_t value,
+ int location)
+{
+ u32 base = blk->base;
+ u32 offset = (location == DSPP) ? PA_VAL_DSPP_OFF : PA_VAL_VIG_OFF;
+ u32 op_val_en = (location == DSPP) ?
+ DSPP_OP_PA_VAL_EN : VIG_OP_PA_VAL_EN;
+ u32 op_pa_en = (location == DSPP) ? DSPP_OP_PA_EN : VIG_OP_PA_EN;
+ u32 disable_req;
+ u32 opmode;
- if (!sat) {
- opmode &= ~VIG_OP_PA_SAT_EN;
- if (PA_DISABLE_REQUIRED(opmode))
- opmode &= ~VIG_OP_PA_EN;
+ SDE_REG_WRITE(hw, base + offset, value & PA_VAL_MASK);
+
+ opmode = SDE_REG_READ(hw, base);
+
+ if (!value) {
+ opmode &= ~op_val_en;
+ disable_req = (location == DSPP) ?
+ PA_DSPP_DISABLE_REQUIRED(opmode) :
+ PA_VIG_DISABLE_REQUIRED(opmode);
+ if (disable_req)
+ opmode &= ~op_pa_en;
} else {
- opmode |= VIG_OP_PA_SAT_EN | VIG_OP_PA_EN;
+ opmode |= op_val_en | op_pa_en;
}
- SDE_REG_WRITE(&ctx->hw, base, opmode);
+ SDE_REG_WRITE(hw, base, opmode);
}
void sde_setup_pipe_pa_val_v1_7(struct sde_hw_pipe *ctx, void *cfg)
{
uint32_t value = *((uint32_t *)cfg);
- u32 base = ctx->cap->sblk->hsic_blk.base;
- u32 opmode = 0;
- SDE_REG_WRITE(&ctx->hw, base + PA_VAL_OFF, value & PA_VAL_MASK);
+ __setup_pa_val(&ctx->hw, &ctx->cap->sblk->hsic_blk, value, SSPP);
+}
- opmode = SDE_REG_READ(&ctx->hw, base);
+static void __setup_pa_cont(struct sde_hw_blk_reg_map *hw,
+ const struct sde_pp_blk *blk, uint32_t contrast,
+ int location)
+{
+ u32 base = blk->base;
+ u32 offset = (location == DSPP) ? PA_CONT_DSPP_OFF : PA_CONT_VIG_OFF;
+ u32 op_cont_en = (location == DSPP) ? DSPP_OP_PA_CONT_EN :
+ VIG_OP_PA_CONT_EN;
+ u32 op_pa_en = (location == DSPP) ? DSPP_OP_PA_EN : VIG_OP_PA_EN;
+ u32 disable_req;
+ u32 opmode;
- if (!value) {
- opmode &= ~VIG_OP_PA_VAL_EN;
- if (PA_DISABLE_REQUIRED(opmode))
- opmode &= ~VIG_OP_PA_EN;
+ SDE_REG_WRITE(hw, base + offset, contrast & PA_CONT_MASK);
+
+ opmode = SDE_REG_READ(hw, base);
+
+ if (!contrast) {
+ opmode &= ~op_cont_en;
+ disable_req = (location == DSPP) ?
+ PA_DSPP_DISABLE_REQUIRED(opmode) :
+ PA_VIG_DISABLE_REQUIRED(opmode);
+ if (disable_req)
+ opmode &= ~op_pa_en;
} else {
- opmode |= VIG_OP_PA_VAL_EN | VIG_OP_PA_EN;
+ opmode |= op_cont_en | op_pa_en;
}
- SDE_REG_WRITE(&ctx->hw, base, opmode);
+ SDE_REG_WRITE(hw, base, opmode);
}
void sde_setup_pipe_pa_cont_v1_7(struct sde_hw_pipe *ctx, void *cfg)
{
uint32_t contrast = *((uint32_t *)cfg);
- u32 base = ctx->cap->sblk->hsic_blk.base;
- u32 opmode = 0;
- SDE_REG_WRITE(&ctx->hw, base + PA_CONT_OFF, contrast & PA_CONT_MASK);
-
- opmode = SDE_REG_READ(&ctx->hw, base);
-
- if (!contrast) {
- opmode &= ~VIG_OP_PA_CONT_EN;
- if (PA_DISABLE_REQUIRED(opmode))
- opmode &= ~VIG_OP_PA_EN;
- } else {
- opmode |= VIG_OP_PA_CONT_EN | VIG_OP_PA_EN;
- }
-
- SDE_REG_WRITE(&ctx->hw, base, opmode);
+ __setup_pa_cont(&ctx->hw, &ctx->cap->sblk->hsic_blk, contrast, SSPP);
}
void sde_setup_pipe_pa_memcol_v1_7(struct sde_hw_pipe *ctx,
@@ -168,7 +286,7 @@
op = SDE_REG_READ(&ctx->hw, base);
if (!mc) {
op &= ~mc_en;
- if (PA_DISABLE_REQUIRED(op))
+ if (PA_VIG_DISABLE_REQUIRED(op))
op &= ~VIG_OP_PA_EN;
SDE_REG_WRITE(&ctx->hw, base, op);
return;
@@ -200,3 +318,136 @@
op |= VIG_OP_PA_EN | mc_en;
SDE_REG_WRITE(&ctx->hw, base, op);
}
+
+void sde_setup_dspp_pcc_v1_7(struct sde_hw_dspp *ctx, void *cfg)
+{
+ struct sde_hw_cp_cfg *hw_cfg = cfg;
+ struct drm_msm_pcc *pcc;
+ void __iomem *base;
+
+ if (!hw_cfg || (hw_cfg->len != sizeof(*pcc) && hw_cfg->payload)) {
+ DRM_ERROR("invalid params hw %p payload %p payloadsize %d \"\
+ exp size %zd\n",
+ hw_cfg, ((hw_cfg) ? hw_cfg->payload : NULL),
+ ((hw_cfg) ? hw_cfg->len : 0), sizeof(*pcc));
+ return;
+ }
+ base = ctx->hw.base_off + ctx->cap->base;
+
+ /* Turn off feature */
+ if (!hw_cfg->payload) {
+ SDE_REG_WRITE(&ctx->hw, ctx->cap->sblk->pcc.base,
+ PCC_OP_MODE_OFF);
+ return;
+ }
+ DRM_DEBUG_DRIVER("Enable PCC feature\n");
+ pcc = hw_cfg->payload;
+
+ SDE_REG_WRITE(&ctx->hw, ctx->cap->sblk->pcc.base + PCC_CONST_COEFF_OFF,
+ pcc->r.c & PCC_CONST_COEFF_MASK);
+ SDE_REG_WRITE(&ctx->hw,
+ ctx->cap->sblk->pcc.base + PCC_CONST_COEFF_OFF + 4,
+ pcc->g.c & PCC_CONST_COEFF_MASK);
+ SDE_REG_WRITE(&ctx->hw,
+ ctx->cap->sblk->pcc.base + PCC_CONST_COEFF_OFF + 8,
+ pcc->b.c & PCC_CONST_COEFF_MASK);
+
+ SDE_REG_WRITE(&ctx->hw, ctx->cap->sblk->pcc.base + PCC_R_COEFF_OFF,
+ pcc->r.r & PCC_COEFF_MASK);
+ SDE_REG_WRITE(&ctx->hw, ctx->cap->sblk->pcc.base + PCC_R_COEFF_OFF + 4,
+ pcc->g.r & PCC_COEFF_MASK);
+ SDE_REG_WRITE(&ctx->hw, ctx->cap->sblk->pcc.base + PCC_R_COEFF_OFF + 8,
+ pcc->b.r & PCC_COEFF_MASK);
+
+ SDE_REG_WRITE(&ctx->hw, ctx->cap->sblk->pcc.base + PCC_G_COEFF_OFF,
+ pcc->r.g & PCC_COEFF_MASK);
+ SDE_REG_WRITE(&ctx->hw, ctx->cap->sblk->pcc.base + PCC_G_COEFF_OFF + 4,
+ pcc->g.g & PCC_COEFF_MASK);
+ SDE_REG_WRITE(&ctx->hw, ctx->cap->sblk->pcc.base + PCC_G_COEFF_OFF + 8,
+ pcc->b.g & PCC_COEFF_MASK);
+
+ SDE_REG_WRITE(&ctx->hw, ctx->cap->sblk->pcc.base + PCC_B_COEFF_OFF,
+ pcc->r.b & PCC_COEFF_MASK);
+ SDE_REG_WRITE(&ctx->hw, ctx->cap->sblk->pcc.base + PCC_B_COEFF_OFF + 4,
+ pcc->g.b & PCC_COEFF_MASK);
+ SDE_REG_WRITE(&ctx->hw, ctx->cap->sblk->pcc.base + PCC_B_COEFF_OFF + 8,
+ pcc->b.b & PCC_COEFF_MASK);
+
+
+ SDE_REG_WRITE(&ctx->hw, ctx->cap->sblk->pcc.base + PCC_RG_COEFF_OFF,
+ pcc->r.rg & PCC_COEFF_MASK);
+ SDE_REG_WRITE(&ctx->hw, ctx->cap->sblk->pcc.base + PCC_RG_COEFF_OFF + 4,
+ pcc->g.rg & PCC_COEFF_MASK);
+ SDE_REG_WRITE(&ctx->hw, ctx->cap->sblk->pcc.base + PCC_RG_COEFF_OFF + 8,
+ pcc->b.rg & PCC_COEFF_MASK);
+
+ SDE_REG_WRITE(&ctx->hw, ctx->cap->sblk->pcc.base + PCC_RB_COEFF_OFF,
+ pcc->r.rb & PCC_COEFF_MASK);
+ SDE_REG_WRITE(&ctx->hw, ctx->cap->sblk->pcc.base + PCC_RB_COEFF_OFF + 4,
+ pcc->g.rb & PCC_COEFF_MASK);
+ SDE_REG_WRITE(&ctx->hw, ctx->cap->sblk->pcc.base + PCC_RB_COEFF_OFF + 8,
+ pcc->b.rb & PCC_COEFF_MASK);
+
+
+ SDE_REG_WRITE(&ctx->hw, ctx->cap->sblk->pcc.base + PCC_GB_COEFF_OFF,
+ pcc->r.gb & PCC_COEFF_MASK);
+ SDE_REG_WRITE(&ctx->hw, ctx->cap->sblk->pcc.base + PCC_GB_COEFF_OFF + 4,
+ pcc->g.gb & PCC_COEFF_MASK);
+ SDE_REG_WRITE(&ctx->hw, ctx->cap->sblk->pcc.base + PCC_GB_COEFF_OFF + 8,
+ pcc->b.gb & PCC_COEFF_MASK);
+
+ SDE_REG_WRITE(&ctx->hw, ctx->cap->sblk->pcc.base + PCC_RGB_COEFF_OFF,
+ pcc->r.rgb & PCC_COEFF_MASK);
+ SDE_REG_WRITE(&ctx->hw,
+ ctx->cap->sblk->pcc.base + PCC_RGB_COEFF_OFF + 4,
+ pcc->g.rgb & PCC_COEFF_MASK);
+ SDE_REG_WRITE(&ctx->hw,
+ ctx->cap->sblk->pcc.base + PCC_RGB_COEFF_OFF + 8,
+ pcc->b.rgb & PCC_COEFF_MASK);
+ SDE_REG_WRITE(&ctx->hw, ctx->cap->sblk->pcc.base, DSPP_OP_PCC_ENABLE);
+}
+
+void sde_setup_dspp_pa_vlut_v1_7(struct sde_hw_dspp *ctx, void *cfg)
+{
+ struct drm_msm_pa_vlut *payload = NULL;
+ struct sde_hw_cp_cfg *hw_cfg = cfg;
+ u32 base = ctx->cap->sblk->vlut.base;
+ u32 offset = base + PA_LUTV_DSPP_OFF;
+ u32 op_mode, tmp;
+ int i = 0, j = 0;
+
+ if (!hw_cfg || (hw_cfg->payload && hw_cfg->len !=
+ sizeof(struct drm_msm_pa_vlut))) {
+ DRM_ERROR("hw %pK payload %pK payloadsize %d exp size %zd\n",
+ hw_cfg, ((hw_cfg) ? hw_cfg->payload : NULL),
+ ((hw_cfg) ? hw_cfg->len : 0),
+ sizeof(struct drm_msm_pa_vlut));
+ return;
+ }
+ op_mode = SDE_REG_READ(&ctx->hw, base);
+ if (!hw_cfg->payload) {
+ DRM_DEBUG_DRIVER("Disable vlut feature\n");
+ /**
+ * In the PA_VLUT disable case, remove PA_VLUT enable bit(19)
+ * first, then check whether any other PA sub-features are
+ * enabled or not. If none of the sub-features are enabled,
+ * remove the PA global enable bit(20).
+ */
+ op_mode &= ~((u32)DSPP_OP_PA_LUTV_EN);
+ if (PA_DSPP_DISABLE_REQUIRED(op_mode))
+ op_mode &= ~((u32)DSPP_OP_PA_EN);
+ SDE_REG_WRITE(&ctx->hw, base, op_mode);
+ return;
+ }
+ payload = hw_cfg->payload;
+ DRM_DEBUG_DRIVER("Enable vlut feature flags %llx\n", payload->flags);
+ for (i = 0, j = 0; i < ARRAY_SIZE(payload->val); i += 2, j += 4) {
+ tmp = (payload->val[i] & REG_MASK(10)) |
+ ((payload->val[i + 1] & REG_MASK(10)) << 16);
+ SDE_REG_WRITE(&ctx->hw, (offset + j),
+ tmp);
+ }
+ SDE_REG_WRITE(&ctx->hw, (base + PA_LUT_SWAP_OFF), 1);
+ op_mode |= DSPP_OP_PA_EN | DSPP_OP_PA_LUTV_EN;
+ SDE_REG_WRITE(&ctx->hw, base, op_mode);
+}
diff --git a/drivers/gpu/drm/msm/sde/sde_hw_color_processing_v1_7.h b/drivers/gpu/drm/msm/sde/sde_hw_color_processing_v1_7.h
index 174ed85..0f9bc0e 100644
--- a/drivers/gpu/drm/msm/sde/sde_hw_color_processing_v1_7.h
+++ b/drivers/gpu/drm/msm/sde/sde_hw_color_processing_v1_7.h
@@ -14,6 +14,7 @@
#define _SDE_HW_COLOR_PROCESSING_V1_7_H
#include "sde_hw_sspp.h"
+#include "sde_hw_dspp.h"
/**
* sde_setup_pipe_pa_hue_v1_7 - setup SSPP hue feature in v1.7 hardware
@@ -53,4 +54,25 @@
enum sde_memcolor_type type,
void *cfg);
+/**
+ * sde_setup_dspp_pcc_v1_7 - setup DSPP PCC veature in v1.7 hardware
+ * @ctx: Pointer to dspp context
+ * @cfg: Pointer to PCC data
+ */
+void sde_setup_dspp_pcc_v1_7(struct sde_hw_dspp *ctx, void *cfg);
+
+/**
+ * sde_setup_dspp_pa_hue_v1_7 - setup DSPP hue feature in v1.7 hardware
+ * @ctx: Pointer to DSPP context
+ * @cfg: Pointer to hue data
+ */
+void sde_setup_dspp_pa_hue_v1_7(struct sde_hw_dspp *ctx, void *cfg);
+
+/**
+ * sde_setup_dspp_pa_vlut_v1_7 - setup DSPP PA vLUT feature in v1.7 hardware
+ * @ctx: Pointer to DSPP context
+ * @cfg: Pointer to vLUT data
+ */
+void sde_setup_dspp_pa_vlut_v1_7(struct sde_hw_dspp *ctx, void *cfg);
+
#endif
diff --git a/drivers/gpu/drm/msm/sde/sde_hw_dspp.c b/drivers/gpu/drm/msm/sde/sde_hw_dspp.c
index 939c833..66c03f0 100644
--- a/drivers/gpu/drm/msm/sde/sde_hw_dspp.c
+++ b/drivers/gpu/drm/msm/sde/sde_hw_dspp.c
@@ -9,46 +9,12 @@
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
-#include "drm/msm_drm_pp.h"
+#include <drm/msm_drm_pp.h>
#include "sde_hw_mdss.h"
#include "sde_hwio.h"
#include "sde_hw_catalog.h"
#include "sde_hw_dspp.h"
-
-#define PCC_ENABLE BIT(0)
-#define PCC_OP_MODE_OFF 0
-#define PCC_CONST_COEFF_OFF 4
-#define PCC_R_COEFF_OFF 0x10
-#define PCC_G_COEFF_OFF 0x1C
-#define PCC_B_COEFF_OFF 0x28
-#define PCC_RG_COEFF_OFF 0x34
-#define PCC_RB_COEFF_OFF 0x40
-#define PCC_GB_COEFF_OFF 0x4C
-#define PCC_RGB_COEFF_OFF 0x58
-#define PCC_CONST_COEFF_MASK 0xFFFF
-#define PCC_COEFF_MASK 0x3FFFF
-
-#define REG_MASK(n) ((BIT(n)) - 1)
-#define PA_SZ_VAL_MASK BIT(31)
-#define PA_SZ_SAT_MASK BIT(30)
-#define PA_SZ_HUE_MASK BIT(29)
-#define PA_CONT_MASK BIT(28)
-#define PA_VAL_MASK BIT(27)
-#define PA_SAT_MASK BIT(26)
-#define PA_HUE_MASK BIT(25)
-#define PA_LUTV_MASK BIT(19)
-#define PA_HIST_MASK BIT(16)
-#define PA_MEM_SKY_MASK BIT(7)
-#define PA_MEM_FOL_MASK BIT(6)
-#define PA_MEM_SKIN_MASK BIT(5)
-#define PA_ENABLE BIT(20)
-
-#define PA_ENABLE_MASK (PA_SZ_VAL_MASK | PA_SZ_SAT_MASK | PA_SZ_HUE_MASK \
- | PA_CONT_MASK | PA_VAL_MASK | PA_SAT_MASK \
- | PA_HUE_MASK | PA_LUTV_MASK | PA_HIST_MASK \
- | PA_MEM_SKY_MASK | PA_MEM_FOL_MASK | PA_MEM_SKIN_MASK)
-
-#define PA_LUT_SWAP_OFF 0x234
+#include "sde_hw_color_processing.h"
static struct sde_dspp_cfg *_dspp_offset(enum sde_dspp dspp,
struct sde_mdss_cfg *m,
@@ -82,157 +48,10 @@
{
}
-void sde_dspp_setup_pa(struct sde_hw_dspp *dspp, void *cfg)
-{
-}
-
-void sde_dspp_setup_hue(struct sde_hw_dspp *dspp, void *cfg)
-{
-}
-
-void sde_dspp_setup_vlut(struct sde_hw_dspp *ctx, void *cfg)
-{
- struct drm_msm_pa_vlut *payload = NULL;
- struct sde_hw_cp_cfg *hw_cfg = cfg;
- u32 op_mode, tmp;
- int i = 0, j = 0;
-
- if (!hw_cfg || (hw_cfg->payload && hw_cfg->len !=
- sizeof(struct drm_msm_pa_vlut))) {
- DRM_ERROR("hw %pK payload %pK payloadsize %d exp size %zd\n",
- hw_cfg, ((hw_cfg) ? hw_cfg->payload : NULL),
- ((hw_cfg) ? hw_cfg->len : 0),
- sizeof(struct drm_msm_pa_vlut));
- return;
- }
- op_mode = SDE_REG_READ(&ctx->hw, 0);
- if (!hw_cfg->payload) {
- DRM_DEBUG_DRIVER("Disable vlut feature\n");
- /**
- * In the PA_VLUT disable case, remove PA_VLUT enable bit(19)
- * first, then check whether any other PA sub-features are
- * enabled or not. If none of the sub-features are enabled,
- * remove the PA global enable bit(20).
- */
- op_mode &= ~((u32)PA_LUTV_MASK);
- if (!(op_mode & PA_ENABLE_MASK))
- op_mode &= ~((u32)PA_ENABLE);
- SDE_REG_WRITE(&ctx->hw, 0, op_mode);
- return;
- }
- payload = hw_cfg->payload;
- DRM_DEBUG_DRIVER("Enable vlut feature flags %llx\n", payload->flags);
- for (i = 0, j = 0; i < ARRAY_SIZE(payload->val); i += 2, j += 4) {
- tmp = (payload->val[i] & REG_MASK(10)) |
- ((payload->val[i + 1] & REG_MASK(10)) << 16);
- SDE_REG_WRITE(&ctx->hw, (ctx->cap->sblk->vlut.base + j),
- tmp);
- }
- SDE_REG_WRITE(&ctx->hw, PA_LUT_SWAP_OFF, 1);
- op_mode |= PA_ENABLE | PA_LUTV_MASK;
- SDE_REG_WRITE(&ctx->hw, 0, op_mode);
-}
-
-void sde_dspp_setup_pcc(struct sde_hw_dspp *ctx, void *cfg)
-{
- struct sde_hw_cp_cfg *hw_cfg = cfg;
- struct drm_msm_pcc *pcc;
- void __iomem *base;
-
- if (!hw_cfg || (hw_cfg->len != sizeof(*pcc) && hw_cfg->payload)) {
- DRM_ERROR(
- "hw_cfg %pK payload %pK payload size %d exp size %zd\n",
- hw_cfg, (hw_cfg ? hw_cfg->payload : NULL),
- ((hw_cfg) ? hw_cfg->len : 0), sizeof(*pcc));
- return;
- }
- base = ctx->hw.base_off + ctx->cap->base;
-
- /* Turn off feature */
- if (!hw_cfg->payload) {
- SDE_REG_WRITE(&ctx->hw, ctx->cap->sblk->pcc.base,
- PCC_OP_MODE_OFF);
- return;
- }
- DRM_DEBUG_DRIVER("Enable PCC feature\n");
- pcc = hw_cfg->payload;
-
- SDE_REG_WRITE(&ctx->hw, ctx->cap->sblk->pcc.base + PCC_CONST_COEFF_OFF,
- pcc->r.c & PCC_CONST_COEFF_MASK);
- SDE_REG_WRITE(&ctx->hw,
- ctx->cap->sblk->pcc.base + PCC_CONST_COEFF_OFF + 4,
- pcc->g.c & PCC_CONST_COEFF_MASK);
- SDE_REG_WRITE(&ctx->hw,
- ctx->cap->sblk->pcc.base + PCC_CONST_COEFF_OFF + 8,
- pcc->b.c & PCC_CONST_COEFF_MASK);
-
- SDE_REG_WRITE(&ctx->hw, ctx->cap->sblk->pcc.base + PCC_R_COEFF_OFF,
- pcc->r.r & PCC_COEFF_MASK);
- SDE_REG_WRITE(&ctx->hw, ctx->cap->sblk->pcc.base + PCC_R_COEFF_OFF + 4,
- pcc->g.r & PCC_COEFF_MASK);
- SDE_REG_WRITE(&ctx->hw, ctx->cap->sblk->pcc.base + PCC_R_COEFF_OFF + 8,
- pcc->b.r & PCC_COEFF_MASK);
-
- SDE_REG_WRITE(&ctx->hw, ctx->cap->sblk->pcc.base + PCC_G_COEFF_OFF,
- pcc->r.g & PCC_COEFF_MASK);
- SDE_REG_WRITE(&ctx->hw, ctx->cap->sblk->pcc.base + PCC_G_COEFF_OFF + 4,
- pcc->g.g & PCC_COEFF_MASK);
- SDE_REG_WRITE(&ctx->hw, ctx->cap->sblk->pcc.base + PCC_G_COEFF_OFF + 8,
- pcc->b.g & PCC_COEFF_MASK);
-
- SDE_REG_WRITE(&ctx->hw, ctx->cap->sblk->pcc.base + PCC_B_COEFF_OFF,
- pcc->r.b & PCC_COEFF_MASK);
- SDE_REG_WRITE(&ctx->hw, ctx->cap->sblk->pcc.base + PCC_B_COEFF_OFF + 4,
- pcc->g.b & PCC_COEFF_MASK);
- SDE_REG_WRITE(&ctx->hw, ctx->cap->sblk->pcc.base + PCC_B_COEFF_OFF + 8,
- pcc->b.b & PCC_COEFF_MASK);
-
-
- SDE_REG_WRITE(&ctx->hw, ctx->cap->sblk->pcc.base + PCC_RG_COEFF_OFF,
- pcc->r.rg & PCC_COEFF_MASK);
- SDE_REG_WRITE(&ctx->hw, ctx->cap->sblk->pcc.base + PCC_RG_COEFF_OFF + 4,
- pcc->g.rg & PCC_COEFF_MASK);
- SDE_REG_WRITE(&ctx->hw, ctx->cap->sblk->pcc.base + PCC_RG_COEFF_OFF + 8,
- pcc->b.rg & PCC_COEFF_MASK);
-
- SDE_REG_WRITE(&ctx->hw, ctx->cap->sblk->pcc.base + PCC_RB_COEFF_OFF,
- pcc->r.rb & PCC_COEFF_MASK);
- SDE_REG_WRITE(&ctx->hw, ctx->cap->sblk->pcc.base + PCC_RB_COEFF_OFF + 4,
- pcc->g.rb & PCC_COEFF_MASK);
- SDE_REG_WRITE(&ctx->hw, ctx->cap->sblk->pcc.base + PCC_RB_COEFF_OFF + 8,
- pcc->b.rb & PCC_COEFF_MASK);
-
-
- SDE_REG_WRITE(&ctx->hw, ctx->cap->sblk->pcc.base + PCC_GB_COEFF_OFF,
- pcc->r.gb & PCC_COEFF_MASK);
- SDE_REG_WRITE(&ctx->hw, ctx->cap->sblk->pcc.base + PCC_GB_COEFF_OFF + 4,
- pcc->g.gb & PCC_COEFF_MASK);
- SDE_REG_WRITE(&ctx->hw, ctx->cap->sblk->pcc.base + PCC_GB_COEFF_OFF + 8,
- pcc->b.gb & PCC_COEFF_MASK);
-
- SDE_REG_WRITE(&ctx->hw, ctx->cap->sblk->pcc.base + PCC_RGB_COEFF_OFF,
- pcc->r.rgb & PCC_COEFF_MASK);
- SDE_REG_WRITE(&ctx->hw,
- ctx->cap->sblk->pcc.base + PCC_RGB_COEFF_OFF + 4,
- pcc->g.rgb & PCC_COEFF_MASK);
- SDE_REG_WRITE(&ctx->hw,
- ctx->cap->sblk->pcc.base + PCC_RGB_COEFF_OFF + 8,
- pcc->b.rgb & PCC_COEFF_MASK);
- SDE_REG_WRITE(&ctx->hw, ctx->cap->sblk->pcc.base, PCC_ENABLE);
-}
-
void sde_dspp_setup_sharpening(struct sde_hw_dspp *ctx, void *cfg)
{
}
-void sde_dspp_setup_pa_memcolor(struct sde_hw_dspp *ctx, void *cfg)
-{
-}
-
-void sde_dspp_setup_sixzone(struct sde_hw_dspp *dspp)
-{
-}
-
void sde_dspp_setup_danger_safe(struct sde_hw_dspp *ctx, void *cfg)
{
}
@@ -252,22 +71,21 @@
case SDE_DSPP_PCC:
if (c->cap->sblk->pcc.version ==
(SDE_COLOR_PROCESS_VER(0x1, 0x7)))
- c->ops.setup_pcc = sde_dspp_setup_pcc;
+ c->ops.setup_pcc = sde_setup_dspp_pcc_v1_7;
break;
case SDE_DSPP_HSIC:
if (c->cap->sblk->hsic.version ==
(SDE_COLOR_PROCESS_VER(0x1, 0x7)))
- c->ops.setup_hue = sde_dspp_setup_hue;
+ c->ops.setup_hue = sde_setup_dspp_pa_hue_v1_7;
break;
case SDE_DSPP_VLUT:
if (c->cap->sblk->vlut.version ==
(SDE_COLOR_PROCESS_VER(0x1, 0x7))) {
- c->ops.setup_vlut = sde_dspp_setup_vlut;
+ c->ops.setup_vlut = sde_setup_dspp_pa_vlut_v1_7;
}
default:
break;
}
-
}
}