commit c7db5c56194711a71d2ce1c3dd0f04e9eb99e56e
author Gopikrishnaiah Anandan <agopik@codeaurora.org> Wed Mar 29 12:16:49 2017 -0700
committer Gerrit - the friendly Code Review server <code-review@localhost> Thu May 18 15:59:22 2017 -0700
tree b9431c7231a49e8d16c181f1971708d062494c29
parent cd4760381dc9ba63455be2ff1b8a281c99f0a584

drm/msm/sde: Fix gamma correction table indexing

Gamma correction table index was incorrectly set which will lead to
color swap issue. Change fixes the index calculation and uses the reg
dma method to set the opcode/swap registers.

Change-Id: Ia0bee41c913108dcb4e70c0dd0701aa0a6bee904
Signed-off-by: Gopikrishnaiah Anandan <agopik@codeaurora.org>

drivers/gpu/drm/msm/sde/sde_hw_reg_dma_v1_color_proc.c

diff --git a/drivers/gpu/drm/msm/sde/sde_hw_reg_dma_v1_color_proc.c b/drivers/gpu/drm/msm/sde/sde_hw_reg_dma_v1_color_proc.c
index c33e520..5719c51 100644
--- a/drivers/gpu/drm/msm/sde/sde_hw_reg_dma_v1_color_proc.c
+++ b/drivers/gpu/drm/msm/sde/sde_hw_reg_dma_v1_color_proc.c
@@ -529,16 +529,36 @@
 		REG_DMA_SETUP_OPS(dma_write_cfg,
 			ctx->cap->sblk->gc.base + GC_C0_OFF +
 			(i * sizeof(u32) * 2),
-			lut_cfg->c0 + ARRAY_SIZE(lut_cfg->c0),
+			lut_cfg->c0 + (ARRAY_SIZE(lut_cfg->c0) * i),
 			PGC_TBL_LEN * sizeof(u32),
 			REG_BLK_WRITE_INC, 0, 0);
 		rc = dma_ops->setup_payload(&dma_write_cfg);
 		if (rc) {
-			DRM_ERROR("index init failed ret %d\n", rc);
+			DRM_ERROR("lut write failed ret %d\n", rc);
 			return;
 		}
 	}
 
+	reg = BIT(0);
+	REG_DMA_SETUP_OPS(dma_write_cfg,
+		ctx->cap->sblk->gc.base + GC_LUT_SWAP_OFF,
+		&reg, sizeof(reg), REG_SINGLE_WRITE, 0, 0);
+	rc = dma_ops->setup_payload(&dma_write_cfg);
+	if (rc) {
+		DRM_ERROR("setting swap offset failed ret %d\n", rc);
+		return;
+	}
+
+	reg = GC_EN | ((lut_cfg->flags & PGC_8B_ROUND) ? GC_8B_ROUND_EN : 0);
+	REG_DMA_SETUP_OPS(dma_write_cfg,
+		ctx->cap->sblk->gc.base,
+		&reg, sizeof(reg), REG_SINGLE_WRITE, 0, 0);
+	rc = dma_ops->setup_payload(&dma_write_cfg);
+	if (rc) {
+		DRM_ERROR("enabling gamma correction failed ret %d\n", rc);
+		return;
+	}
+
 	REG_DMA_SETUP_KICKOFF(kick_off, hw_cfg->ctl, dspp_buf[GC][ctx->idx],
 			REG_DMA_WRITE, DMA_CTL_QUEUE0, WRITE_IMMEDIATE);
 	kick_off.last_command = hw_cfg->last_feature;
@@ -547,11 +567,6 @@
 		DRM_ERROR("failed to kick off ret %d\n", rc);
 		return;
 	}
-
-	reg = GC_EN | ((lut_cfg->flags & PGC_8B_ROUND) ? GC_8B_ROUND_EN : 0);
-	SDE_REG_WRITE(&ctx->hw, ctx->cap->sblk->gc.base + GC_LUT_SWAP_OFF,
-			BIT(0));
-	SDE_REG_WRITE(&ctx->hw, ctx->cap->sblk->gc.base, reg);
 }
 
 int reg_dmav1_deinit_dspp_ops(enum sde_dspp idx)