| commit | c8d0953084f6981ccfb1c1ef48f118407da0b836 | [log] [tgz] |
|---|---|---|
| author | Vara Reddy <varar@codeaurora.org> | Mon Sep 04 23:42:44 2017 -0700 |
| committer | Vara Reddy <varar@codeaurora.org> | Thu Sep 07 05:43:54 2017 -0700 |
| tree | 3238e5f8cb10645a9bb979e5fe7a0c02cd34f129 | |
| parent | 6d6d60c0800afb56bcc21c014dc8ac218c72c0cd [diff] |
clk: mdss: adjust PLL disable sequence to avoid glitch Adjust the PLL disable sequence as per the latest HW programming guidelines to ensure there will not be any stray clock glitches when PLL is turned OFF abruptly. Change-Id: I3636d09df4e86601e8b5189db1ad088a66f83489 Signed-off-by: Vara Reddy <varar@codeaurora.org>