tree f9443de1d4534b0b56bd1b0ff56bfc6d78eb698d
parent 2f135eaf182761bb9a5cbd5138a447b0ad2a1fef
author Paul Walmsley <paul@pwsan.com> 1245460106 -0600
committer paul <paul@twilight.(none)> 1245460171 -0600

OMAP3 clock: add a short delay when lowering CORE clk rate

When changing the SDRAM clock from 166MHz to 83MHz via the CORE DPLL M2
divider, add a short delay before returning to SDRAM to allow the SDRC
time to stabilize.  Without this delay, the system is prone to random
panics upon re-entering SDRAM.

This time delay varies based on MPU frequency.  At 500MHz MPU frequency at
room temperature, 64 loops seems to work okay; so add another 32 loops for
environmental and process variation.

Signed-off-by: Paul Walmsley <paul@pwsan.com>