tree ca3b1ac67a4ad722b45d5714a36176c44972b310
parent 98b32decc83ed3137e3ddbc918b102f8fc406b6d
author Nick Kossifidis <mickflemm@gmail.com> 1386382660 +0000
committer John W. Linville <linville@tuxdriver.com> 1386777382 -0500

ath5k: Reset Tx interrupt bits also on PISR

Some cards don't update the PISR properly when all SISR bits
for Tx interrupts are being cleared and as a result we get
interrupt storm. Since we handle all tx queues all together
(so we don't really use the SISR bits to do per-queue interrupt
handling), we can manualy update PISR by doing a write-to-clear
on its Tx interrupt bits.

Signed-off-by: Nick Kossifidis <mickflemm@gmail.com>
Signed-off-by: John W. Linville <linville@tuxdriver.com>