tg3: Allow DMAs to cross cacheline boundaries
By default, the 5717 (and future chips) break up PCIe DMA packets across
cacheline boundaries. This isn't necessary on x86. This patch
selectively loosens the restriction.
Signed-off-by: Matt Carlson <mcarlson@broadcom.com>
Reviewed-by: Michael Chan <mchan@broadcom.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
diff --git a/drivers/net/tg3.h b/drivers/net/tg3.h
index e7916bd..42fefa1 100644
--- a/drivers/net/tg3.h
+++ b/drivers/net/tg3.h
@@ -142,8 +142,7 @@
#define METAL_REV_B1 0x01
#define METAL_REV_B2 0x02
#define TG3PCI_DMA_RW_CTRL 0x0000006c
-#define DMA_RWCTRL_MIN_DMA 0x000000ff
-#define DMA_RWCTRL_MIN_DMA_SHIFT 0
+#define DMA_RWCTRL_DIS_CACHE_ALIGNMENT 0x00000001
#define DMA_RWCTRL_READ_BNDRY_MASK 0x00000700
#define DMA_RWCTRL_READ_BNDRY_DISAB 0x00000000
#define DMA_RWCTRL_READ_BNDRY_16 0x00000100