tree 5ef904efcb61988c273f4987cd2bc86c772cdec9
parent 42365cf0fa19473dde5fe226b0e7e9ab8ea18af8
author Rabin Vincent <rabin.vincent@stericsson.com> 1337242658 +0530
committer Fabio Baltieri <fabio.baltieri@linaro.org> 1358157037 +0100

dmaengine: ste_dma40: don't allow high priority dest event lines

Hardware bug: when a logical channel is triggerred by a high priority
destination event line, an extra packet transaction is generated in case
of important data write response latency on previous logical channel A
and if the source transfer of current logical channel B is already
completed and if no other channel with a higher priority than B is
waiting for execution.

Software workaround: do not set the high priority level for the
destination event lines that trigger logical channels.

Signed-off-by: Rabin Vincent <rabin.vincent@stericsson.com>
Reviewed-by: Shreshtha Kumar Sahu <shreshthakumar.sahu@stericsson.com>
Acked-by: Linus Walleij <linus.walleij@linaro.org>
Acked-by: Vinod Koul <vinod.koul@intel.com>
Signed-off-by: Fabio Baltieri <fabio.baltieri@linaro.org>