| commit | ccd6385dfbb7b2f2e6670b5cfc55bb7ec0aa3839 | [log] [tgz] |
|---|---|---|
| author | Marc Zyngier <marc.zyngier@arm.com> | Wed Jul 15 11:55:18 2015 +0100 |
| committer | Will Deacon <will.deacon@arm.com> | Fri Jul 31 11:38:14 2015 +0100 |
| tree | d150fda1fe2cfd5868b2c8aeb3d0de88fdb248a7 | |
| parent | cbfe8fa6cd672011c755c3cd85c9ffd4e2d10a6f [diff] |
iommu/arm-smmu: Fix enabling of PRIQ interrupt When an ARM SMMUv3 instance supports PRI, the driver registers an interrupt handler, but fails to enable the generation of such interrupt at the SMMU level. This patches simply moves the enable flags to a variable that gets updated by the PRI handling code before being written to the SMMU register. Signed-off-by: Marc Zyngier <marc.zyngier@arm.com> Signed-off-by: Will Deacon <will.deacon@arm.com>