tree 8190ebc04222bf5a05e5bbc81c07d2d51f1a7616
parent 84d727a109081684c2e01b811cb0d6dc3b9380ca
author Stefan Roese <sr@denx.de> 1228442329 +0000
committer Josh Boyer <jwboyer@linux.vnet.ibm.com> 1229007782 -0500

powerpc/4xx: Add L2 cache node to AMCC Canyonlands dts file

With this patch the L2 cache is enabled on Canyonlands to increase the
overall performance. There is a known cache coherency issue with the L2
cache, but this is related to the high bandwidth (HB) PLB segment where
the memory address is 0x8.xxxx.xxxx (low bandwidth PLB segment is mapped
to 0x0.xxxx.xxxx). Since this HB address is currently unused it is safe
to enable the L2 cache.

Signed-off-by: Stefan Roese <sr@denx.de>
Signed-off-by: Josh Boyer <jwboyer@linux.vnet.ibm.com>