| commit | ce3887ed0d996e6353d739e8139b8e5faeb726d5 | [log] [tgz] |
|---|---|---|
| author | Mark Yao <mark.yao@rock-chips.com> | Wed Dec 16 18:08:17 2015 +0800 |
| committer | Mark Yao <mark.yao@rock-chips.com> | Mon Dec 28 08:49:48 2015 +0800 |
| tree | c6093d90fbeb7d2ac9a4cb6d8a7f60714a64b17c | |
| parent | 63ebb9fa7ff06d194362ed4a5d0a31ac7612a89c [diff] |
drm/rockchip: Optimization vop mode set Rk3288 vop timing registers is immediately register, when configure timing on display active time, will cause tearing. use dclk reset is not a good idea to avoid this tearing. we can avoid tearing by using standby register. Vop standby register will take effect at end of current frame, and go back to work immediately when exit standby. So we can use standby register to protect this context. Signed-off-by: Mark Yao <mark.yao@rock-chips.com>