blob: 2a61e1847a3564d7538a1f7b3e8a5b00648b7815 [file] [log] [blame]
/* Copyright (c) 2017, The Linux Foundation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 and
* only version 2 as published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#include "dsi-panel-sim-video.dtsi"
#include "dsi-panel-sim-cmd.dtsi"
#include "dsi-panel-sim-dsc375-cmd.dtsi"
#include "dsi-panel-sim-dualmipi-video.dtsi"
#include "dsi-panel-sim-dualmipi-cmd.dtsi"
#include "dsi-panel-sim-dualmipi-dsc375-cmd.dtsi"
#include "dsi-panel-nt35597-truly-dualmipi-wqxga-video.dtsi"
#include "dsi-panel-nt35597-truly-dualmipi-wqxga-cmd.dtsi"
#include "dsi-panel-nt35597-truly-dsc-wqxga-cmd.dtsi"
#include "dsi-panel-nt35597-truly-dsc-wqxga-video.dtsi"
#include "dsi-panel-nt35597-dualmipi-wqxga-video.dtsi"
#include "dsi-panel-nt35597-dualmipi-wqxga-cmd.dtsi"
#include "dsi-panel-nt35695b-truly-fhd-video.dtsi"
#include "dsi-panel-nt35695b-truly-fhd-cmd.dtsi"
#include "dsi-panel-rm67195-amoled-fhd-cmd.dtsi"
#include <dt-bindings/clock/mdss-10nm-pll-clk.h>
&soc {
dsi_panel_pwr_supply: dsi_panel_pwr_supply {
#address-cells = <1>;
#size-cells = <0>;
qcom,panel-supply-entry@0 {
reg = <0>;
qcom,supply-name = "vddio";
qcom,supply-min-voltage = <1800000>;
qcom,supply-max-voltage = <1800000>;
qcom,supply-enable-load = <62000>;
qcom,supply-disable-load = <80>;
qcom,supply-post-on-sleep = <20>;
};
qcom,panel-supply-entry@1 {
reg = <1>;
qcom,supply-name = "lab";
qcom,supply-min-voltage = <4600000>;
qcom,supply-max-voltage = <6000000>;
qcom,supply-enable-load = <100000>;
qcom,supply-disable-load = <100>;
};
qcom,panel-supply-entry@2 {
reg = <2>;
qcom,supply-name = "ibb";
qcom,supply-min-voltage = <4600000>;
qcom,supply-max-voltage = <6000000>;
qcom,supply-enable-load = <100000>;
qcom,supply-disable-load = <100>;
qcom,supply-post-on-sleep = <20>;
};
};
dsi_panel_pwr_supply_no_labibb: dsi_panel_pwr_supply_no_labibb {
#address-cells = <1>;
#size-cells = <0>;
qcom,panel-supply-entry@0 {
reg = <0>;
qcom,supply-name = "vddio";
qcom,supply-min-voltage = <1800000>;
qcom,supply-max-voltage = <1800000>;
qcom,supply-enable-load = <62000>;
qcom,supply-disable-load = <80>;
qcom,supply-post-on-sleep = <20>;
};
};
dsi_panel_pwr_supply_vdd_no_labibb: dsi_panel_pwr_supply_vdd_no_labibb {
#address-cells = <1>;
#size-cells = <0>;
qcom,panel-supply-entry@0 {
reg = <0>;
qcom,supply-name = "vddio";
qcom,supply-min-voltage = <1800000>;
qcom,supply-max-voltage = <1800000>;
qcom,supply-enable-load = <62000>;
qcom,supply-disable-load = <80>;
qcom,supply-post-on-sleep = <20>;
};
qcom,panel-supply-entry@1 {
reg = <1>;
qcom,supply-name = "vdd";
qcom,supply-min-voltage = <3000000>;
qcom,supply-max-voltage = <3000000>;
qcom,supply-enable-load = <857000>;
qcom,supply-disable-load = <0>;
qcom,supply-post-on-sleep = <0>;
};
};
dsi_panel_pwr_supply_labibb_amoled: dsi_panel_pwr_supply_labibb_amoled {
#address-cells = <1>;
#size-cells = <0>;
qcom,panel-supply-entry@0 {
reg = <0>;
qcom,supply-name = "wqhd-vddio";
qcom,supply-min-voltage = <1800000>;
qcom,supply-max-voltage = <1950000>;
qcom,supply-enable-load = <32000>;
qcom,supply-disable-load = <80>;
};
qcom,panel-supply-entry@1 {
reg = <1>;
qcom,supply-name = "vdda-3p3";
qcom,supply-min-voltage = <3300000>;
qcom,supply-max-voltage = <3300000>;
qcom,supply-enable-load = <13200>;
qcom,supply-disable-load = <80>;
};
qcom,panel-supply-entry@2 {
reg = <2>;
qcom,supply-name = "lab";
qcom,supply-min-voltage = <4600000>;
qcom,supply-max-voltage = <6100000>;
qcom,supply-enable-load = <100000>;
qcom,supply-disable-load = <100>;
};
qcom,panel-supply-entry@3 {
reg = <3>;
qcom,supply-name = "ibb";
qcom,supply-min-voltage = <4000000>;
qcom,supply-max-voltage = <6300000>;
qcom,supply-enable-load = <100000>;
qcom,supply-disable-load = <100>;
};
qcom,panel-supply-entry@4 {
reg = <4>;
qcom,supply-name = "oledb";
qcom,supply-min-voltage = <5000000>;
qcom,supply-max-voltage = <8100000>;
qcom,supply-enable-load = <100000>;
qcom,supply-disable-load = <100>;
};
};
dsi_dual_nt35597_truly_video_display: qcom,dsi-display@0 {
compatible = "qcom,dsi-display";
label = "dsi_dual_nt35597_truly_video_display";
qcom,display-type = "primary";
qcom,dsi-ctrl = <&mdss_dsi0 &mdss_dsi1>;
qcom,dsi-phy = <&mdss_dsi_phy0 &mdss_dsi_phy1>;
clocks = <&mdss_dsi0_pll BYTECLK_MUX_0_CLK>,
<&mdss_dsi0_pll PCLK_MUX_0_CLK>;
clock-names = "src_byte_clk", "src_pixel_clk";
pinctrl-names = "panel_active", "panel_suspend";
pinctrl-0 = <&sde_dsi_active &sde_te_active>;
pinctrl-1 = <&sde_dsi_suspend &sde_te_suspend>;
qcom,platform-reset-gpio = <&tlmm 75 0>;
qcom,panel-mode-gpio = <&tlmm 76 0>;
qcom,dsi-panel = <&dsi_dual_nt35597_truly_video>;
vddio-supply = <&pm660_l11>;
lab-supply = <&lcdb_ldo_vreg>;
ibb-supply = <&lcdb_ncp_vreg>;
};
dsi_dual_nt35597_truly_cmd_display: qcom,dsi-display@1 {
compatible = "qcom,dsi-display";
label = "dsi_dual_nt35597_truly_cmd_display";
qcom,display-type = "primary";
qcom,dsi-ctrl = <&mdss_dsi0 &mdss_dsi1>;
qcom,dsi-phy = <&mdss_dsi_phy0 &mdss_dsi_phy1>;
clocks = <&mdss_dsi0_pll BYTECLK_MUX_0_CLK>,
<&mdss_dsi0_pll PCLK_MUX_0_CLK>;
clock-names = "src_byte_clk", "src_pixel_clk";
pinctrl-names = "panel_active", "panel_suspend";
pinctrl-0 = <&sde_dsi_active &sde_te_active>;
pinctrl-1 = <&sde_dsi_suspend &sde_te_suspend>;
qcom,platform-te-gpio = <&tlmm 10 0>;
qcom,platform-reset-gpio = <&tlmm 75 0>;
qcom,panel-mode-gpio = <&tlmm 76 0>;
qcom,dsi-panel = <&dsi_dual_nt35597_truly_cmd>;
vddio-supply = <&pm660_l11>;
lab-supply = <&lcdb_ldo_vreg>;
ibb-supply = <&lcdb_ncp_vreg>;
};
dsi_nt35597_truly_dsc_cmd_display: qcom,dsi-display@2 {
compatible = "qcom,dsi-display";
label = "dsi_nt35597_truly_dsc_cmd_display";
qcom,display-type = "primary";
qcom,dsi-ctrl = <&mdss_dsi1>;
qcom,dsi-phy = <&mdss_dsi_phy1>;
clocks = <&mdss_dsi1_pll BYTECLK_MUX_1_CLK>,
<&mdss_dsi1_pll PCLK_MUX_1_CLK>;
clock-names = "src_byte_clk", "src_pixel_clk";
pinctrl-names = "panel_active", "panel_suspend";
pinctrl-0 = <&sde_dsi_active &sde_te_active>;
pinctrl-1 = <&sde_dsi_suspend &sde_te_suspend>;
qcom,platform-te-gpio = <&tlmm 10 0>;
qcom,platform-reset-gpio = <&tlmm 75 0>;
qcom,panel-mode-gpio = <&tlmm 76 0>;
qcom,dsi-panel = <&dsi_nt35597_truly_dsc_cmd>;
vddio-supply = <&pm660_l11>;
lab-supply = <&lcdb_ldo_vreg>;
ibb-supply = <&lcdb_ncp_vreg>;
};
dsi_nt35597_truly_dsc_video_display: qcom,dsi-display@3 {
compatible = "qcom,dsi-display";
label = "dsi_nt35597_truly_dsc_video_display";
qcom,display-type = "primary";
qcom,dsi-ctrl = <&mdss_dsi1>;
qcom,dsi-phy = <&mdss_dsi_phy1>;
clocks = <&mdss_dsi1_pll BYTECLK_MUX_1_CLK>,
<&mdss_dsi1_pll PCLK_MUX_1_CLK>;
clock-names = "src_byte_clk", "src_pixel_clk";
pinctrl-names = "panel_active", "panel_suspend";
pinctrl-0 = <&sde_dsi_active &sde_te_active>;
pinctrl-1 = <&sde_dsi_suspend &sde_te_suspend>;
qcom,platform-te-gpio = <&tlmm 10 0>;
qcom,platform-reset-gpio = <&tlmm 75 0>;
qcom,panel-mode-gpio = <&tlmm 76 0>;
qcom,dsi-panel = <&dsi_nt35597_truly_dsc_video>;
vddio-supply = <&pm660_l11>;
lab-supply = <&lcdb_ldo_vreg>;
ibb-supply = <&lcdb_ncp_vreg>;
};
dsi_sim_vid_display: qcom,dsi-display@4 {
compatible = "qcom,dsi-display";
label = "dsi_sim_vid_display";
qcom,display-type = "primary";
qcom,dsi-ctrl = <&mdss_dsi0>;
qcom,dsi-phy = <&mdss_dsi_phy0>;
clocks = <&mdss_dsi0_pll BYTECLK_MUX_0_CLK>,
<&mdss_dsi0_pll PCLK_MUX_0_CLK>;
clock-names = "src_byte_clk", "src_pixel_clk";
pinctrl-names = "panel_active", "panel_suspend";
pinctrl-0 = <&sde_dsi_active &sde_te_active>;
pinctrl-1 = <&sde_dsi_suspend &sde_te_suspend>;
qcom,dsi-panel = <&dsi_sim_vid>;
};
dsi_dual_sim_vid_display: qcom,dsi-display@5 {
compatible = "qcom,dsi-display";
label = "dsi_dual_sim_vid_display";
qcom,display-type = "primary";
qcom,dsi-ctrl = <&mdss_dsi0 &mdss_dsi1>;
qcom,dsi-phy = <&mdss_dsi_phy0 &mdss_dsi_phy1>;
clocks = <&mdss_dsi0_pll BYTECLK_MUX_0_CLK>,
<&mdss_dsi0_pll PCLK_MUX_0_CLK>;
clock-names = "src_byte_clk", "src_pixel_clk";
pinctrl-names = "panel_active", "panel_suspend";
pinctrl-0 = <&sde_dsi_active &sde_te_active>;
pinctrl-1 = <&sde_dsi_suspend &sde_te_suspend>;
qcom,dsi-panel = <&dsi_dual_sim_vid>;
};
dsi_sim_cmd_display: qcom,dsi-display@6 {
compatible = "qcom,dsi-display";
label = "dsi_sim_cmd_display";
qcom,display-type = "primary";
qcom,dsi-ctrl = <&mdss_dsi0>;
qcom,dsi-phy = <&mdss_dsi_phy0>;
clocks = <&mdss_dsi0_pll BYTECLK_MUX_0_CLK>,
<&mdss_dsi0_pll PCLK_MUX_0_CLK>;
clock-names = "src_byte_clk", "src_pixel_clk";
pinctrl-names = "panel_active", "panel_suspend";
pinctrl-0 = <&sde_dsi_active &sde_te_active>;
pinctrl-1 = <&sde_dsi_suspend &sde_te_suspend>;
qcom,dsi-panel = <&dsi_sim_cmd>;
};
dsi_dual_sim_cmd_display: qcom,dsi-display@7 {
compatible = "qcom,dsi-display";
label = "dsi_dual_sim_cmd_display";
qcom,display-type = "primary";
qcom,dsi-ctrl = <&mdss_dsi0 &mdss_dsi1>;
qcom,dsi-phy = <&mdss_dsi_phy0 &mdss_dsi_phy1>;
clocks = <&mdss_dsi0_pll BYTECLK_MUX_0_CLK>,
<&mdss_dsi0_pll PCLK_MUX_0_CLK>;
clock-names = "src_byte_clk", "src_pixel_clk";
pinctrl-names = "panel_active", "panel_suspend";
pinctrl-0 = <&sde_dsi_active &sde_te_active>;
pinctrl-1 = <&sde_dsi_suspend &sde_te_suspend>;
qcom,dsi-panel = <&dsi_dual_sim_cmd>;
};
dsi_sim_dsc_375_cmd_display: qcom,dsi-display@8 {
compatible = "qcom,dsi-display";
label = "dsi_sim_dsc_375_cmd_display";
qcom,display-type = "primary";
qcom,dsi-ctrl = <&mdss_dsi0>;
qcom,dsi-phy = <&mdss_dsi_phy0>;
clocks = <&mdss_dsi0_pll BYTECLK_MUX_0_CLK>,
<&mdss_dsi0_pll PCLK_MUX_0_CLK>;
clock-names = "src_byte_clk", "src_pixel_clk";
pinctrl-names = "panel_active", "panel_suspend";
pinctrl-0 = <&sde_dsi_active &sde_te_active>;
pinctrl-1 = <&sde_dsi_suspend &sde_te_suspend>;
qcom,dsi-panel = <&dsi_sim_dsc_375_cmd>;
};
dsi_dual_sim_dsc_375_cmd_display: qcom,dsi-display@9 {
compatible = "qcom,dsi-display";
label = "dsi_dual_sim_dsc_375_cmd_display";
qcom,display-type = "primary";
qcom,dsi-ctrl = <&mdss_dsi0 &mdss_dsi1>;
qcom,dsi-phy = <&mdss_dsi_phy0 &mdss_dsi_phy1>;
clocks = <&mdss_dsi0_pll BYTECLK_MUX_0_CLK>,
<&mdss_dsi0_pll PCLK_MUX_0_CLK>;
clock-names = "src_byte_clk", "src_pixel_clk";
pinctrl-names = "panel_active", "panel_suspend";
pinctrl-0 = <&sde_dsi_active &sde_te_active>;
pinctrl-1 = <&sde_dsi_suspend &sde_te_suspend>;
qcom,dsi-panel = <&dsi_dual_sim_dsc_375_cmd>;
};
dsi_dual_nt35597_video_display: qcom,dsi-display@10 {
compatible = "qcom,dsi-display";
label = "dsi_dual_nt35597_video_display";
qcom,display-type = "primary";
qcom,dsi-ctrl = <&mdss_dsi0 &mdss_dsi1>;
qcom,dsi-phy = <&mdss_dsi_phy0 &mdss_dsi_phy1>;
clocks = <&mdss_dsi0_pll BYTECLK_MUX_0_CLK>,
<&mdss_dsi0_pll PCLK_MUX_0_CLK>;
clock-names = "src_byte_clk", "src_pixel_clk";
pinctrl-names = "panel_active", "panel_suspend";
pinctrl-0 = <&sde_dsi_active &sde_te_active>;
pinctrl-1 = <&sde_dsi_suspend &sde_te_suspend>;
qcom,platform-reset-gpio = <&tlmm 75 0>;
qcom,panel-mode-gpio = <&tlmm 76 0>;
qcom,dsi-panel = <&dsi_dual_nt35597_video>;
vddio-supply = <&pm660_l11>;
lab-supply = <&lcdb_ldo_vreg>;
ibb-supply = <&lcdb_ncp_vreg>;
};
dsi_dual_nt35597_cmd_display: qcom,dsi-display@11 {
compatible = "qcom,dsi-display";
label = "dsi_dual_nt35597_cmd_display";
qcom,display-type = "primary";
qcom,dsi-ctrl = <&mdss_dsi0 &mdss_dsi1>;
qcom,dsi-phy = <&mdss_dsi_phy0 &mdss_dsi_phy1>;
clocks = <&mdss_dsi0_pll BYTECLK_MUX_0_CLK>,
<&mdss_dsi0_pll PCLK_MUX_0_CLK>;
clock-names = "src_byte_clk", "src_pixel_clk";
pinctrl-names = "panel_active", "panel_suspend";
pinctrl-0 = <&sde_dsi_active &sde_te_active>;
pinctrl-1 = <&sde_dsi_suspend &sde_te_suspend>;
qcom,platform-reset-gpio = <&tlmm 75 0>;
qcom,panel-mode-gpio = <&tlmm 76 0>;
qcom,dsi-panel = <&dsi_dual_nt35597_cmd>;
vddio-supply = <&pm660_l11>;
lab-supply = <&lcdb_ldo_vreg>;
ibb-supply = <&lcdb_ncp_vreg>;
};
dsi_rm67195_amoled_fhd_cmd_display: qcom,dsi-display@12 {
compatible = "qcom,dsi-display";
label = "dsi_rm67195_amoled_fhd_cmd_display";
qcom,display-type = "primary";
qcom,dsi-ctrl = <&mdss_dsi0>;
qcom,dsi-phy = <&mdss_dsi_phy0>;
clocks = <&mdss_dsi0_pll BYTECLK_MUX_0_CLK>,
<&mdss_dsi0_pll PCLK_MUX_0_CLK>;
clock-names = "src_byte_clk", "src_pixel_clk";
pinctrl-names = "panel_active", "panel_suspend";
pinctrl-0 = <&sde_dsi_active &sde_te_active>;
pinctrl-1 = <&sde_dsi_suspend &sde_te_suspend>;
qcom,platform-te-gpio = <&tlmm 10 0>;
qcom,platform-reset-gpio = <&tlmm 75 0>;
qcom,dsi-panel = <&dsi_rm67195_amoled_fhd_cmd>;
vddio-supply = <&pm660_l11>;
lab-supply = <&lcdb_ldo_vreg>;
ibb-supply = <&lcdb_ncp_vreg>;
};
dsi_nt35695b_truly_fhd_video_display: qcom,dsi-display@13 {
compatible = "qcom,dsi-display";
label = "dsi_nt35695b_truly_fhd_video_display";
qcom,display-type = "primary";
qcom,dsi-ctrl = <&mdss_dsi0>;
qcom,dsi-phy = <&mdss_dsi_phy0>;
clocks = <&mdss_dsi0_pll BYTECLK_MUX_0_CLK>,
<&mdss_dsi0_pll PCLK_MUX_0_CLK>;
clock-names = "src_byte_clk", "src_pixel_clk";
pinctrl-names = "panel_active", "panel_suspend";
pinctrl-0 = <&sde_dsi_active &sde_te_active>;
pinctrl-1 = <&sde_dsi_suspend &sde_te_suspend>;
qcom,platform-reset-gpio = <&tlmm 75 0>;
qcom,dsi-panel = <&dsi_nt35695b_truly_fhd_video>;
vddio-supply = <&pm660_l11>;
lab-supply = <&lcdb_ldo_vreg>;
ibb-supply = <&lcdb_ncp_vreg>;
};
dsi_nt35695b_truly_fhd_cmd_display: qcom,dsi-display@14 {
compatible = "qcom,dsi-display";
label = "dsi_nt35695b_truly_fhd_cmd_display";
qcom,display-type = "primary";
qcom,dsi-ctrl = <&mdss_dsi0>;
qcom,dsi-phy = <&mdss_dsi_phy0>;
clocks = <&mdss_dsi0_pll BYTECLK_MUX_0_CLK>,
<&mdss_dsi0_pll PCLK_MUX_0_CLK>;
clock-names = "src_byte_clk", "src_pixel_clk";
pinctrl-names = "panel_active", "panel_suspend";
pinctrl-0 = <&sde_dsi_active &sde_te_active>;
pinctrl-1 = <&sde_dsi_suspend &sde_te_suspend>;
qcom,platform-te-gpio = <&tlmm 10 0>;
qcom,platform-reset-gpio = <&tlmm 75 0>;
qcom,dsi-panel = <&dsi_nt35695b_truly_fhd_cmd>;
vddio-supply = <&pm660_l11>;
lab-supply = <&lcdb_ldo_vreg>;
ibb-supply = <&lcdb_ncp_vreg>;
};
sde_wb: qcom,wb-display@0 {
compatible = "qcom,wb-display";
cell-index = <0>;
label = "wb_display";
};
ext_disp: qcom,msm-ext-disp {
compatible = "qcom,msm-ext-disp";
ext_disp_audio_codec: qcom,msm-ext-disp-audio-codec-rx {
compatible = "qcom,msm-ext-disp-audio-codec-rx";
};
};
sde_dp: qcom,dp_display@0{
cell-index = <0>;
compatible = "qcom,dp-display";
gdsc-supply = <&mdss_core_gdsc>;
vdda-1p2-supply = <&pm660_l1>;
vdda-0p9-supply = <&pm660l_l1>;
reg = <0xae90000 0xa84>,
<0x88eaa00 0x200>,
<0x88ea200 0x200>,
<0x88ea600 0x200>,
<0xaf02000 0x1a0>,
<0x780000 0x621c>,
<0x88ea030 0x10>,
<0x88e8000 0x20>,
<0x0aee1000 0x034>;
reg-names = "dp_ctrl", "dp_phy", "dp_ln_tx0", "dp_ln_tx1",
"dp_mmss_cc", "qfprom_physical", "dp_pll",
"usb3_dp_com", "hdcp_physical";
interrupt-parent = <&mdss_mdp>;
interrupts = <12 0>;
clocks = <&clock_dispcc DISP_CC_MDSS_DP_AUX_CLK>,
<&clock_rpmh RPMH_CXO_CLK>,
<&clock_gcc GCC_USB3_PRIM_CLKREF_CLK>,
<&clock_gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>,
<&clock_gcc GCC_USB3_PRIM_PHY_PIPE_CLK>,
<&clock_dispcc DISP_CC_MDSS_DP_LINK_CLK>,
<&clock_dispcc DISP_CC_MDSS_DP_LINK_INTF_CLK>,
<&clock_dispcc DISP_CC_MDSS_DP_PIXEL_CLK>,
<&clock_dispcc DISP_CC_MDSS_DP_CRYPTO_CLK>,
<&clock_dispcc DISP_CC_MDSS_DP_PIXEL_CLK_SRC>,
<&mdss_dp_pll DP_VCO_DIVIDED_CLK_SRC_MUX>;
clock-names = "core_aux_clk", "core_usb_ref_clk_src",
"core_usb_ref_clk", "core_usb_cfg_ahb_clk",
"core_usb_pipe_clk", "ctrl_link_clk",
"ctrl_link_iface_clk", "ctrl_pixel_clk",
"crypto_clk", "pixel_clk_rcg", "pixel_parent";
qcom,dp-usbpd-detection = <&pm660_pdphy>;
qcom,ext-disp = <&ext_disp>;
qcom,aux-cfg0-settings = [20 00];
qcom,aux-cfg1-settings = [24 13 23 1d];
qcom,aux-cfg2-settings = [28 24];
qcom,aux-cfg3-settings = [2c 00];
qcom,aux-cfg4-settings = [30 0a];
qcom,aux-cfg5-settings = [34 26];
qcom,aux-cfg6-settings = [38 0a];
qcom,aux-cfg7-settings = [3c 03];
qcom,aux-cfg8-settings = [40 bb];
qcom,aux-cfg9-settings = [44 03];
qcom,max-pclk-frequency-khz = <675000>;
qcom,core-supply-entries {
#address-cells = <1>;
#size-cells = <0>;
qcom,core-supply-entry@0 {
reg = <0>;
qcom,supply-name = "gdsc";
qcom,supply-min-voltage = <0>;
qcom,supply-max-voltage = <0>;
qcom,supply-enable-load = <0>;
qcom,supply-disable-load = <0>;
};
};
qcom,ctrl-supply-entries {
#address-cells = <1>;
#size-cells = <0>;
qcom,ctrl-supply-entry@0 {
reg = <0>;
qcom,supply-name = "vdda-1p2";
qcom,supply-min-voltage = <1200000>;
qcom,supply-max-voltage = <1200000>;
qcom,supply-enable-load = <21800>;
qcom,supply-disable-load = <4>;
};
};
qcom,phy-supply-entries {
#address-cells = <1>;
#size-cells = <0>;
qcom,phy-supply-entry@0 {
reg = <0>;
qcom,supply-name = "vdda-0p9";
qcom,supply-min-voltage = <880000>;
qcom,supply-max-voltage = <880000>;
qcom,supply-enable-load = <36000>;
qcom,supply-disable-load = <32>;
};
};
};
};
&sde_dp {
pinctrl-names = "mdss_dp_active", "mdss_dp_sleep";
pinctrl-0 = <&sde_dp_aux_active &sde_dp_usbplug_cc_active>;
pinctrl-1 = <&sde_dp_aux_suspend &sde_dp_usbplug_cc_suspend>;
qcom,aux-en-gpio = <&tlmm 50 0>;
qcom,aux-sel-gpio = <&tlmm 40 0>;
qcom,usbplug-cc-gpio = <&tlmm 38 0>;
};
&mdss_mdp {
connectors = <&sde_rscc &sde_wb &sde_dp>;
};
&dsi_dual_nt35597_truly_video {
qcom,mdss-dsi-t-clk-post = <0x0D>;
qcom,mdss-dsi-t-clk-pre = <0x2D>;
qcom,mdss-dsi-display-timings {
timing@0{
qcom,mdss-dsi-panel-phy-timings = [00 1c 07 07 23 21 07
07 05 03 04 00];
qcom,display-topology = <2 0 2>,
<1 0 2>;
qcom,default-topology-index = <0>;
};
};
};
&dsi_dual_nt35597_truly_cmd {
qcom,mdss-dsi-t-clk-post = <0x0D>;
qcom,mdss-dsi-t-clk-pre = <0x2D>;
qcom,mdss-dsi-display-timings {
timing@0{
qcom,mdss-dsi-panel-phy-timings = [00 1c 07 07 23 21 07
07 05 03 04 00];
qcom,display-topology = <2 0 2>,
<1 0 2>;
qcom,default-topology-index = <0>;
};
};
};
&dsi_nt35597_truly_dsc_cmd {
qcom,mdss-dsi-t-clk-post = <0x0b>;
qcom,mdss-dsi-t-clk-pre = <0x23>;
qcom,mdss-dsi-display-timings {
timing@0{
qcom,mdss-dsi-panel-phy-timings = [00 15 05 05 20 1f 05
05 03 03 04 00];
qcom,display-topology = <1 1 1>,
<2 2 1>, /* dsc merge */
<2 1 1>; /* 3d mux */
qcom,default-topology-index = <1>;
};
};
};
&dsi_nt35597_truly_dsc_video {
qcom,mdss-dsi-t-clk-post = <0x0b>;
qcom,mdss-dsi-t-clk-pre = <0x23>;
qcom,mdss-dsi-display-timings {
timing@0{
qcom,mdss-dsi-panel-phy-timings = [00 15 05 05 20 1f 05
04 03 03 04 00];
qcom,display-topology = <1 1 1>,
<2 2 1>, /* dsc merge */
<2 1 1>; /* 3d mux */
qcom,default-topology-index = <1>;
};
};
};
&dsi_sim_vid {
qcom,mdss-dsi-t-clk-post = <0x0d>;
qcom,mdss-dsi-t-clk-pre = <0x2d>;
qcom,mdss-dsi-display-timings {
timing@0{
qcom,mdss-dsi-panel-phy-timings = [00 1c 07 07 23 21 07
07 05 03 04 00];
qcom,display-topology = <1 0 1>,
<2 0 1>;
qcom,default-topology-index = <0>;
};
};
};
&dsi_dual_sim_vid {
qcom,mdss-dsi-t-clk-post = <0x0d>;
qcom,mdss-dsi-t-clk-pre = <0x2d>;
qcom,mdss-dsi-display-timings {
timing@0{
qcom,mdss-dsi-panel-phy-timings = [00 1c 07 07 23 21 07
07 05 03 04 00];
qcom,display-topology = <2 0 2>,
<1 0 2>;
qcom,default-topology-index = <0>;
};
};
};
&dsi_sim_cmd {
qcom,mdss-dsi-t-clk-post = <0x0d>;
qcom,mdss-dsi-t-clk-pre = <0x2d>;
qcom,mdss-dsi-display-timings {
timing@0{
qcom,mdss-dsi-panel-phy-timings = [00 1c 07 07 23 21 07
07 05 03 04 00];
qcom,display-topology = <1 0 1>,
<2 0 1>;
qcom,default-topology-index = <0>;
};
};
};
&dsi_dual_sim_cmd {
qcom,mdss-dsi-t-clk-post = <0x0d>;
qcom,mdss-dsi-t-clk-pre = <0x2d>;
qcom,mdss-dsi-display-timings {
timing@0{
qcom,mdss-dsi-panel-phy-timings = [00 24 09 09 26 24 09
09 06 03 04 00];
qcom,display-topology = <2 0 2>;
qcom,default-topology-index = <0>;
};
timing@1{
qcom,mdss-dsi-panel-phy-timings = [00 1c 07 07 23 21 07
07 05 03 04 00];
qcom,display-topology = <2 0 2>,
<1 0 2>;
qcom,default-topology-index = <0>;
};
timing@2{
qcom,mdss-dsi-panel-phy-timings = [00 18 06 06 21 20 06
06 04 03 04 00];
qcom,display-topology = <2 0 2>;
qcom,default-topology-index = <0>;
};
};
};
&dsi_sim_dsc_375_cmd {
qcom,mdss-dsi-t-clk-post = <0x0d>;
qcom,mdss-dsi-t-clk-pre = <0x2d>;
qcom,mdss-dsi-display-timings {
timing@0 { /* 1080p */
qcom,mdss-dsi-panel-phy-timings = [00 1A 06 06 22 20 07
07 04 03 04 00];
qcom,display-topology = <1 1 1>;
qcom,default-topology-index = <0>;
};
timing@1 { /* qhd */
qcom,mdss-dsi-panel-phy-timings = [00 15 05 05 20 1f 05
05 03 03 04 00];
qcom,display-topology = <1 1 1>,
<2 2 1>, /* dsc merge */
<2 1 1>; /* 3d mux */
qcom,default-topology-index = <0>;
};
};
};
&dsi_dual_sim_dsc_375_cmd {
qcom,mdss-dsi-t-clk-post = <0x0d>;
qcom,mdss-dsi-t-clk-pre = <0x2d>;
qcom,mdss-dsi-display-timings {
timing@0 { /* qhd */
qcom,mdss-dsi-panel-phy-timings = [00 1c 07 07 23 21 07
07 05 03 04 00];
qcom,display-topology = <2 2 2>;
qcom,default-topology-index = <0>;
};
timing@1 { /* 4k */
qcom,mdss-dsi-panel-phy-timings = [00 18 06 06 21 20 06
06 04 03 04 00];
qcom,display-topology = <2 2 2>;
qcom,default-topology-index = <0>;
};
};
};
&dsi_dual_nt35597_video {
qcom,mdss-dsi-t-clk-post = <0x0d>;
qcom,mdss-dsi-t-clk-pre = <0x2d>;
qcom,mdss-dsi-display-timings {
timing@0 {
qcom,mdss-dsi-panel-timings = [00 1c 08 07 23 22 07 07
05 03 04 00];
qcom,display-topology = <2 0 2>,
<1 0 2>;
qcom,default-topology-index = <0>;
};
};
};
&dsi_dual_nt35597_cmd {
qcom,mdss-dsi-t-clk-post = <0x0d>;
qcom,mdss-dsi-t-clk-pre = <0x2d>;
qcom,mdss-dsi-display-timings {
timing@0 {
qcom,mdss-dsi-panel-timings = [00 1c 08 07 23 22 07 07
05 03 04 00];
qcom,display-topology = <2 0 2>,
<1 0 2>;
qcom,default-topology-index = <0>;
};
};
};
&dsi_rm67195_amoled_fhd_cmd {
qcom,mdss-dsi-t-clk-post = <0x07>;
qcom,mdss-dsi-t-clk-pre = <0x1c>;
qcom,mdss-dsi-display-timings {
timing@0 {
qcom,mdss-dsi-panel-phy-timings = [00 1c 05 06 0b 0c
05 07 05 03 04 00];
qcom,display-topology = <1 0 1>;
qcom,default-topology-index = <0>;
};
};
};
&dsi_nt35695b_truly_fhd_video {
qcom,mdss-dsi-t-clk-post = <0x07>;
qcom,mdss-dsi-t-clk-pre = <0x1c>;
qcom,mdss-dsi-display-timings {
timing@0 {
qcom,mdss-dsi-panel-phy-timings = [00 1c 05 06 0b 0c
05 07 05 03 04 00];
qcom,display-topology = <1 0 1>;
qcom,default-topology-index = <0>;
};
};
};
&dsi_nt35695b_truly_fhd_cmd {
qcom,mdss-dsi-t-clk-post = <0x07>;
qcom,mdss-dsi-t-clk-pre = <0x1c>;
qcom,mdss-dsi-display-timings {
timing@0 {
qcom,mdss-dsi-panel-phy-timings = [00 1c 05 06 0b 0c
05 07 05 03 04 00];
qcom,display-topology = <1 0 1>;
qcom,default-topology-index = <0>;
};
};
};