| commit | d0a312455698f5efd1f3ec72bcfe8d58490bbe0a | [log] [tgz] |
|---|---|---|
| author | Aditya Bavanari <abavanar@codeaurora.org> | Wed Apr 26 16:15:07 2017 +0530 |
| committer | Banajit Goswami <bgoswami@codeaurora.org> | Tue Jun 13 09:26:40 2017 -0700 |
| tree | 8ef44528a69232a815d195a55eb3165bb759f2a1 | |
| parent | 3fa8397e80defffc049ad98a0511761b2db12cb6 [diff] |
ASoC: sdm660_cdc: Update volatile register set for cache bypass Update the volatile register set for cache bypassing. Set only required registers as volatile and others as non volatile in order to enable register read from cache. CRs-Fixed: 2031818 Change-Id: Ib53798a3f81fc133f6f3902f7bac750cca1cabc6 Signed-off-by: Aditya Bavanari <abavanar@codeaurora.org>