tree ba270d4a8ca0666bd753f3bad9088a113730452a
parent fbeb91fe8e4107dc88df4eaa21de02c3fd9d1cd5
author Andy Shevchenko <andriy.shevchenko@linux.intel.com> 1399539708 +0300
committer Vinod Koul <vinod.koul@intel.com> 1400753244 +0530

dmaengine: dw: enable clock before access

hclk signal is a bus clock. So, it means we have to have it enabled during
access to the DMA controller. This patch makes sure that we enable clock before
access to the device, though it currently works on Intel hardware.

Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Signed-off-by: Vinod Koul <vinod.koul@intel.com>