| commit | d331328da6b719e4ffb3b43125bbe540755239ad | [log] [tgz] |
|---|---|---|
| author | Andre Przywara <andre.przywara@arm.com> | Tue Feb 16 10:46:08 2016 +0000 |
| committer | Maxime Ripard <maxime.ripard@free-electrons.com> | Sun Feb 21 19:44:49 2016 -0800 |
| tree | c2d7afe11f2676edb6f4e76eee6fa362fbe6ca08 | |
| parent | b26803ebfba8d81e2e8fb392c1248df2ebd1ba83 [diff] |
clk: sunxi: Improve divs_clk error handling and reporting We catch errors in the base clock registration, failure to ioremap and failures in the final of_clk_add_provider() call. Also we unmap the registers when we need to rollback. Signed-off-by: Andre Przywara <andre.przywara@arm.com> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>