diff --git a/drivers/gpu/msm/adreno.c b/drivers/gpu/msm/adreno.c
index 9425ea3..4dd3932 100644
--- a/drivers/gpu/msm/adreno.c
+++ b/drivers/gpu/msm/adreno.c
@@ -111,6 +111,7 @@
 	.active_list = LIST_HEAD_INIT(device_3d0.active_list),
 	.active_list_lock = __SPIN_LOCK_UNLOCKED(device_3d0.active_list_lock),
 	.gpu_llc_slice_enable = true,
+	.gpuhtw_llc_slice_enable = true,
 };
 
 /* Ptr to array for the current set of fault detect registers */
diff --git a/drivers/gpu/msm/adreno.h b/drivers/gpu/msm/adreno.h
index 6278c7b..929de48 100644
--- a/drivers/gpu/msm/adreno.h
+++ b/drivers/gpu/msm/adreno.h
@@ -399,6 +399,7 @@
  * @gpu_llc_slice: GPU system cache slice descriptor
  * @gpu_llc_slice_enable: To enable the GPU system cache slice or not
  * @gpuhtw_llc_slice: GPU pagetables system cache slice descriptor
+ * @gpuhtw_llc_slice_enable: To enable the GPUHTW system cache slice or not
  */
 struct adreno_device {
 	struct kgsl_device dev;    /* Must be first field in this struct */
@@ -461,6 +462,7 @@
 	void *gpu_llc_slice;
 	bool gpu_llc_slice_enable;
 	void *gpuhtw_llc_slice;
+	bool gpuhtw_llc_slice_enable;
 };
 
 /**
diff --git a/drivers/gpu/msm/adreno_llc.h b/drivers/gpu/msm/adreno_llc.h
index 16c2e4e..90dff82 100644
--- a/drivers/gpu/msm/adreno_llc.h
+++ b/drivers/gpu/msm/adreno_llc.h
@@ -54,7 +54,7 @@
 				gpudev->llc_configure_gpu_scid(adreno_dev);
 		}
 
-	if (adreno_dev->gpuhtw_llc_slice)
+	if (adreno_dev->gpuhtw_llc_slice && adreno_dev->gpuhtw_llc_slice_enable)
 		if (!llcc_slice_activate(adreno_dev->gpuhtw_llc_slice)) {
 			if (gpudev->llc_configure_gpuhtw_scid)
 				gpudev->llc_configure_gpuhtw_scid(adreno_dev);
diff --git a/drivers/gpu/msm/adreno_sysfs.c b/drivers/gpu/msm/adreno_sysfs.c
index db2b585..89ea1d9 100644
--- a/drivers/gpu/msm/adreno_sysfs.c
+++ b/drivers/gpu/msm/adreno_sysfs.c
@@ -89,6 +89,19 @@
 	return adreno_dev->gpu_llc_slice_enable;
 }
 
+static int _gpuhtw_llc_slice_enable_store(struct adreno_device *adreno_dev,
+		unsigned int val)
+{
+	adreno_dev->gpuhtw_llc_slice_enable = val ? true : false;
+	return 0;
+}
+
+static unsigned int
+_gpuhtw_llc_slice_enable_show(struct adreno_device *adreno_dev)
+{
+	return adreno_dev->gpuhtw_llc_slice_enable;
+}
+
 static int _ft_long_ib_detect_store(struct adreno_device *adreno_dev,
 		unsigned int val)
 {
@@ -303,6 +316,7 @@
 static ADRENO_SYSFS_BOOL(ft_long_ib_detect);
 static ADRENO_SYSFS_BOOL(ft_hang_intr_status);
 static ADRENO_SYSFS_BOOL(gpu_llc_slice_enable);
+static ADRENO_SYSFS_BOOL(gpuhtw_llc_slice_enable);
 
 static DEVICE_INT_ATTR(wake_nice, 0644, adreno_wake_nice);
 static DEVICE_INT_ATTR(wake_timeout, 0644, adreno_wake_timeout);
@@ -328,6 +342,7 @@
 	&adreno_attr_hwcg.attr,
 	&adreno_attr_throttling.attr,
 	&adreno_attr_gpu_llc_slice_enable.attr,
+	&adreno_attr_gpuhtw_llc_slice_enable.attr,
 	NULL,
 };