tree 2fb488efa592b5aad68e7ec482d86a6c06741cdf
parent df863de19fc5a7b3a982a8204f9e2e8bb6e2d96d
author Gregory CLEMENT <gregory.clement@free-electrons.com> 1392647003 +0100
committer Jason Cooper <jason@lakedaemon.net> 1393029670 +0000

ARM: mvebu: add initial support for the Armada 375 SOCs

This commit adds the basic support for the Armada 375 SOCs. These SoCs
share most of their IP with the Armada 370/XP SoCs. The main
difference is the use of a Cortex A9 CPU instead of the PJ4B CPU. The
interrupt controller and the L2 cache controller are also different
they are respectively the GIC and the PL310.

The support is introduced in board-v7.c, together with Armada 370/XP,
but a separate DT structure is added, because Armada 375 will need a
different set of SMP operations when the SMP support is introduced.

Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Signed-off-by: Jason Cooper <jason@lakedaemon.net>