tree 822c90b7035c77d445a5329fec3318dab09541b5
parent 3396e7361159753047965d1ed134ff7af248d64c
author Gregory CLEMENT <gregory.clement@free-electrons.com> 1422531384 +0100
committer Ulf Hansson <ulf.hansson@linaro.org> 1422533261 +0100

mmc: sdhci-pxav3: Fix SDR50 and DDR50 capabilities for the Armada 38x flavor

According to erratum 'FE-2946959' both SDR50 and DDR50 modes require
specific clock adjustments in SDIO3 Configuration register. However,
this register was not part of the device tree binding. Even if the
binding can (and will) be extended we still need handling the case
where this register was not available. In this case we use the
SDHCI_QUIRK_MISSING_CAPS quirk remove them from the capabilities.

This commit is based on the work done by Marcin Wojtas<mw@semihalf.com>

Fixes: 5491ce3f79ee ("mmc: sdhci-pxav3: add support for the Armada 38x SDHCI controller")
Cc: <stable@vger.kernel.org> # v3.15+
Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
Signed-off-by: Marcin Wojtas <mw@semihalf.com>
Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>