| commit | d584c1331d6421e2387eab10b11fa6f08b4a4b5f | [log] [tgz] |
|---|---|---|
| author | Emilio López <emilio@elopez.com.ar> | Mon Dec 23 00:32:37 2013 -0300 |
| committer | Emilio López <emilio@elopez.com.ar> | Sat Dec 28 17:08:17 2013 -0300 |
| tree | 7c1d6a78ae45ac0aed61a96ae856f9cd295f70a3 | |
| parent | 5f4e0be3a72325fbc4d349a847cc9b2edd85b6d2 [diff] |
clk: sunxi: add PLL5 and PLL6 support This commit implements PLL5 and PLL6 support on the sunxi clock driver. These PLLs use a similar factor clock, but differ on their outputs. Signed-off-by: Emilio López <emilio@elopez.com.ar> Acked-by: Mike Turquette <mturquette@linaro.org>