| commit | 00c674e42c278e7af7b39b6c72dbbaa5e7ebd96c | [log] [tgz] |
|---|---|---|
| author | Thierry Reding <thierry.reding@gmail.com> | Mon Nov 18 16:11:35 2013 +0100 |
| committer | Peter De Schrijver <pdeschrijver@nvidia.com> | Tue Nov 26 18:44:00 2013 +0200 |
| tree | 72308d5561ffefccd18e45524a6f27817e2271d1 | |
| parent | 480fe6f4cb35d1a3bd14c41736924a97f28346bb [diff] |
clk: tegra: Fix clock rate computation The PLL output frequency is multiplied during the P-divider computation, so it needs to be divided by the P-divider again before returning. This fixes an issue where clk_round_rate() would return the multiplied frequency instead of the real one after the P-divider. Signed-off-by: Thierry Reding <treding@nvidia.com>