tree b153fd653e8704d2cfad2e1cbd923692932a7dde
parent fda7c362f9ef59de6d6db67a854e1a114af0c69a
author Tomi Valkeinen <tomi.valkeinen@ti.com> 1348488906 +0300
committer Tomi Valkeinen <tomi.valkeinen@ti.com> 1348494607 +0300

OMAPDSS: DSI: improve DSI clock calcs for DISPC

Commit ee144e645a081daad5de1ccac77f0a0e98e6a67b added
dsi_pll_calc_ddrfreq() which calculates PLL dividers based on given DSI
bus clock speed. The function works ok, but it can be improved for the
DISPC clock calc.

The current version calculates the clock going from the PLL to the DISPC
simply by setting the clock as close to DISPC maximum as possible, and
the pixel clock is calculated based on that.

This patch changes the function to calculate DISPC clock more
dynamically, iterating through different DISPC clocks and pixel clock
values, and thus we'll get more suitable pixel clocks.

Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>