| commit | b8fc2f6a18052194c486b407765a4f5e4dca692d | [log] [tgz] |
|---|---|---|
| author | Paulo Zanoni <paulo.r.zanoni@intel.com> | Tue Oct 23 18:30:05 2012 -0200 |
| committer | Daniel Vetter <daniel.vetter@ffwll.ch> | Fri Oct 26 10:24:50 2012 +0200 |
| tree | 1a1db94b0ffb90cd25d65ae8e419acbd6673e8c7 | |
| parent | e6f0bfc4fb963da9e945ebc6330db9a4d756ba78 [diff] |
drm/i915: set the correct eDP aux channel clock divider on DDI The cdclk frequency is not always the same, so the value here should be adjusted to match it. Version 2: call intel_ddi_get_cdclk_freq instead of reading CDCLK_FREQ, because the register is just for earlier HW steppings. Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com> Reviewed-by: Rodrigo Vivi <rodrigo.vivi@gmail.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>