| commit | d72f9d919a60e5096105237a72f046b7a20fb53f | [log] [tgz] |
|---|---|---|
| author | Rodrigo Vivi <rodrigo.vivi@intel.com> | Thu Nov 05 10:50:19 2015 -0800 |
| committer | Daniel Vetter <daniel.vetter@ffwll.ch> | Wed Nov 18 11:21:50 2015 +0100 |
| tree | 49b1567648709da74c95288918d9b747d2471c7b | |
| parent | a03bc7cd633760ae0312327b6e30ec8fe962a798 [diff] |
drm/i915: Allow 1 vblank to let Sink CRC calculation to start or stop. According to VESA DP Spec, setting TEST_SINK_START (bit 0) of TEST_SINK (00270h) "Stop/Start calculating CRC on the next frame" So let's wait at least 1 vblank to really say the calculation stopped or started. Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com> Reviewed-by: Paulo Zanoni <paulo.r.zanoni@intel.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>